From dd152da5c2f3e2fe908bf351953e355f0b52558f Mon Sep 17 00:00:00 2001 From: Eren Dogan Date: Tue, 1 Aug 2023 11:26:25 -0700 Subject: [PATCH] Change signal escape router's high-level function name --- compiler/modules/sram_1bank.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 997666df..a230936f 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -367,10 +367,10 @@ class sram_1bank(design, verilog, lef): pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) from openram.router import signal_escape_router as router - rtr=router(layers=self.m3_stack, - design=self, - bbox=bbox) - rtr.escape_route(pins_to_route) + rtr = router(layers=self.m3_stack, + design=self, + bbox=bbox) + rtr.route(pins_to_route) def compute_bus_sizes(self): """ Compute the independent bus widths shared between two and four bank SRAMs """