mirror of https://github.com/VLSIDA/OpenRAM.git
Change signal escape router's high-level function name
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@ -367,10 +367,10 @@ class sram_1bank(design, verilog, lef):
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pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
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pins_to_route.append("spare_wen{0}[{1}]".format(port, bit))
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from openram.router import signal_escape_router as router
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from openram.router import signal_escape_router as router
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rtr=router(layers=self.m3_stack,
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rtr = router(layers=self.m3_stack,
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design=self,
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design=self,
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bbox=bbox)
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bbox=bbox)
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rtr.escape_route(pins_to_route)
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rtr.route(pins_to_route)
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def compute_bus_sizes(self):
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def compute_bus_sizes(self):
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""" Compute the independent bus widths shared between two and four bank SRAMs """
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""" Compute the independent bus widths shared between two and four bank SRAMs """
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