mirror of https://github.com/VLSIDA/OpenRAM.git
Characterizer wmask check for write_size
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@ -183,7 +183,8 @@ class lib:
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# set the read and write port as inputs.
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self.write_data_bus(port)
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self.write_addr_bus(port)
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if self.sram.write_size and port in self.write_ports:
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if self.sram.write_size != self.sram.word_size and \
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port in self.write_ports:
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self.write_wmask_bus(port)
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# need to split this into sram and port control signals
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self.write_control_pins(port)
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@ -378,7 +379,7 @@ class lib:
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self.lib.write(" bit_to : 0;\n")
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self.lib.write(" }\n\n")
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if self.sram.write_size:
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if self.sram.write_size != self.sram.word_size:
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self.lib.write(" type (wmask){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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