From e92337ddaffa27c8eddabd2a9f6579c2e9304ad9 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 Aug 2020 17:08:48 -0700 Subject: [PATCH 1/2] Separate get_ and get_all for bitlines and wordlines --- compiler/modules/bank.py | 16 ++-------- compiler/modules/local_bitcell_array.py | 2 +- compiler/modules/replica_bitcell_array.py | 31 ++++++++++++++++++- compiler/tests/15_local_bitcell_array_test.py | 2 +- 4 files changed, 34 insertions(+), 17 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c5c02869..ba6e4a4e 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -393,21 +393,9 @@ class bank(design.design): # vdd # gnd - temp = [] - - temp.extend(self.bitcell_array.get_dummy_bitline_names(0)) - temp.extend(self.bitcell_array.get_rbl_bitline_names(0)) - temp.extend(self.bitcell_array.get_bitline_names()) - if len(self.all_ports) > 1: - temp.extend(self.bitcell_array.get_rbl_bitline_names(1)) - temp.extend(self.bitcell_array.get_dummy_bitline_names(1)) + temp = self.bitcell_array.get_all_bitline_names() - wordline_names = self.bitcell_array.get_dummy_wordline_names(0) - wordline_names.extend(self.bitcell_array.get_rbl_wordline_names(0)) - wordline_names.extend(self.bitcell_array.get_wordline_names()) - if len(self.all_ports) > 1: - wordline_names.extend(self.bitcell_array.get_rbl_wordline_names(1)) - wordline_names.extend(self.bitcell_array.get_dummy_wordline_names(1)) + wordline_names = self.bitcell_array.get_all_wordline_names() # Rename the RBL WL to the enable name for port in self.all_ports: diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index b199d438..53f0684f 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -104,7 +104,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): # Connect unused RBL WL to gnd array_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("rbl")]) dummy_rbl_names = set([x for x in self.bitcell_array.get_all_wordline_names() if x.startswith("dummy")]) - rbl_wl_names = set([self.bitcell_array.get_rbl_wordline_names(x) for x in self.all_ports]) + rbl_wl_names = set([x for port in self.all_ports for x in self.bitcell_array.get_rbl_wordline_names(port)]) self.gnd_wl_names = list((array_rbl_names - rbl_wl_names) | dummy_rbl_names) self.all_array_wordline_inputs = [x + "i" if x not in self.gnd_wl_names else "gnd" for x in self.bitcell_array.get_wordline_names()] diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 4ebebb67..5ad41b9f 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -471,12 +471,41 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): return self.rbl_bitline_names[port] def get_bitline_names(self, port=None): - """ Return the BL for the given RBL port """ + """ Return the regular bitlines for the given port or all""" if port == None: return self.all_bitline_names else: return self.bitline_names[port] + def get_all_bitline_names(self): + """ Return ALL the bitline names (including dummy and rbl) """ + temp = [] + temp.extend(self.get_dummy_bitline_names(0)) + temp.extend(self.get_rbl_bitline_names(0)) + temp.extend(self.get_bitline_names()) + if len(self.all_ports) > 1: + temp.extend(self.get_rbl_bitline_names(1)) + temp.extend(self.get_dummy_bitline_names(1)) + return temp + + def get_wordline_names(self, port=None): + """ Return the regular wordline names """ + if port == None: + return self.all_wordline_names + else: + return self.wordline_names[port] + + def get_all_wordline_names(self): + """ Return all the wordline names """ + temp = [] + temp.extend(self.get_dummy_wordline_names(0)) + temp.extend(self.get_rbl_wordline_names(0)) + temp.extend(self.all_wordline_names) + if len(self.all_ports) > 1: + temp.extend(self.rbl_wordline_names(1)) + temp.extend(self.get_dummy_wordline_names(1)) + return temp + def get_dummy_wordline_names(self, port=None): """ Return the ACTIVE WL for the given dummy port. diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py index d1cc4c16..591b0607 100755 --- a/compiler/tests/15_local_bitcell_array_test.py +++ b/compiler/tests/15_local_bitcell_array_test.py @@ -15,7 +15,7 @@ from sram_factory import factory import debug -@unittest.skip("SKIPPING 05_local_bitcell_array_test") +# @unittest.skip("SKIPPING 05_local_bitcell_array_test") class local_bitcell_array_test(openram_test): def runTest(self): From c321d8559508eb1638a50691fb2e32f7983c170d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 Aug 2020 09:54:41 -0700 Subject: [PATCH 2/2] Fix syntax error for dual port --- compiler/modules/replica_bitcell_array.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 5ad41b9f..14d7c858 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -495,14 +495,17 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): else: return self.wordline_names[port] - def get_all_wordline_names(self): + def get_all_wordline_names(self, port=None): """ Return all the wordline names """ temp = [] temp.extend(self.get_dummy_wordline_names(0)) temp.extend(self.get_rbl_wordline_names(0)) - temp.extend(self.all_wordline_names) + if port == None: + temp.extend(self.all_wordline_names) + else: + temp.extend(self.wordline_names[port]) if len(self.all_ports) > 1: - temp.extend(self.rbl_wordline_names(1)) + temp.extend(self.get_rbl_wordline_names(1)) temp.extend(self.get_dummy_wordline_names(1)) return temp