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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
Remove EOL whitespace globally
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@@ -23,7 +23,7 @@ class precharge_array(design.design):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
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self.columns = columns
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self.offsets = offsets
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self.size = size
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@@ -35,7 +35,7 @@ class precharge_array(design.design):
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self.en_bar_layer = "m3"
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else:
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self.en_bar_layer = "m1"
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@@ -61,10 +61,10 @@ class precharge_array(design.design):
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self.add_modules()
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self.add_pins()
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self.create_insts()
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def create_layout(self):
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self.place_insts()
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self.width = self.offsets[-1] + self.pc_cell.width
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self.height = self.pc_cell.height
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@@ -94,12 +94,12 @@ class precharge_array(design.design):
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to_layer=self.en_bar_layer,
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offset=inst.get_pin("en_bar").center())
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self.copy_layout_pin(inst, "vdd")
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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self.copy_layout_pin(inst, "bl", "bl_{0}".format(i))
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self.copy_layout_pin(inst, "br", "br_{0}".format(i))
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def create_insts(self):
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"""Creates a precharge array by horizontally tiling the precharge cell"""
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self.local_insts = []
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@@ -114,7 +114,7 @@ class precharge_array(design.design):
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def place_insts(self):
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""" Places precharge array by horizontally tiling the precharge cell"""
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# Default to single spaced columns
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if not self.offsets:
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self.offsets = [n * self.pc_cell.width for n in range(self.columns)]
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@@ -130,4 +130,4 @@ class precharge_array(design.design):
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offset = vector(tempx, 0)
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self.local_insts[i].place(offset=offset, mirror=mirror)
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