Remove EOL whitespace globally

compiler/modules/orig_bitcell_array.py

@@ -27,7 +27,7 @@ class bitcell_array(bitcell_base_array):
         # We don't offset this because we need to align
         # the replica bitcell in the control logic
         # self.offset_all_coordinates()
-        
+
     def create_netlist(self):
         """ Create and connect the netlist """
         self.add_modules()
@@ -41,7 +41,7 @@ class bitcell_array(bitcell_base_array):
         self.add_layout_pins()
 
         self.add_boundary()
-        
+
         self.DRC_LVS()
 
     def add_modules(self):
@@ -58,20 +58,20 @@ class bitcell_array(bitcell_base_array):
                 self.cell_inst[row, col]=self.add_inst(name=name,
                                                        mod=self.cell)
                 self.connect_inst(self.get_bitcell_pins(col, row))
-        
+
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
-        
+
         # Dynamic Power from Bitline
         bl_wire = self.gen_bl_wire()
         cell_load = 2 * bl_wire.return_input_cap()
         bl_swing = OPTS.rbl_delay_percentage
         freq = spice["default_event_frequency"]
         bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
-        
+
         # Calculate the bitcell power which currently only includes leakage
         cell_power = self.cell.analytical_power(corner, load)
-        
+
         # Leakage power grows with entire array and bitlines.
         total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
                                         cell_power.leakage * self.column_size * self.row_size)
@@ -102,7 +102,7 @@ class bitcell_array(bitcell_base_array):
         bitcell_wl_cin = self.cell.get_wl_cin()
         total_cin = bitcell_wl_cin * self.column_size
         return total_cin
-        
+
     def graph_exclude_bits(self, targ_row, targ_col):
         """Excludes bits in column from being added to graph except target"""
         # Function is not robust with column mux configurations
@@ -111,7 +111,7 @@ class bitcell_array(bitcell_base_array):
                 if row == targ_row and col == targ_col:
                     continue
                 self.graph_inst_exclude.add(self.cell_inst[row, col])
-            
+
     def get_cell_name(self, inst_name, row, col):
         """Gets the spice name of the target bitcell."""
         return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]