mirror of https://github.com/VLSIDA/OpenRAM.git
Don't autodetect the bitcell if the user overrides it
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@ -168,8 +168,10 @@ def setup_bitcell():
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if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0):
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if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0):
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OPTS.bitcell = "bitcell"
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OPTS.bitcell = "bitcell"
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OPTS.replica_bitcell = "replica_bitcell"
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OPTS.replica_bitcell = "replica_bitcell"
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# If we have non-1rw ports, figure out the right bitcell to use
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# If we have non-1rw ports,
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else:
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# and the user didn't over-ride the bitcell manually,
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# figure out the right bitcell to use
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elsif (OPTs.bitcell=="bitcell" and OPTS.replica_bitcell=="replica_bitcell"):
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ports = ""
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ports = ""
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if OPTS.num_rw_ports>0:
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if OPTS.num_rw_ports>0:
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ports += "{}rw_".format(OPTS.num_rw_ports)
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ports += "{}rw_".format(OPTS.num_rw_ports)
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