From da48b8d98c6babf816fd7e2ab2bd29dc6703d246 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 14 Dec 2020 14:18:39 -0800 Subject: [PATCH] Fix replica column bit index --- compiler/modules/replica_column.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 2a333c8e..15d71685 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -180,7 +180,7 @@ class replica_column(bitcell_base_array): for port in self.all_ports: for row in range(row_range_min, row_range_max): wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port)) - self.add_layout_pin(text="wl_{0}_{1}".format(port, row), + self.add_layout_pin(text="wl_{0}_{1}".format(port, row - row_range_min), layer=wl_pin.layer, offset=wl_pin.ll().scale(0, 1), width=self.width,