From d92c7a634dc845bcb3306f9260181305c894b06e Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 Jul 2022 10:57:56 -0700 Subject: [PATCH] Use packages for imports. Must set PYTHONPATH to include OPENRAM_HOME now. Reorganizes subdirs as packages. Rewrites unit tests to use packages. Update README.md with instructions, dependencies etc. Update sky130 module imports. Change tech specific package from modules to custom. --- README.md | 56 ++- compiler/base/__init__.py | 21 ++ compiler/base/channel_route.py | 6 +- compiler/base/contact.py | 60 +-- compiler/base/design.py | 205 +---------- compiler/base/geometry.py | 4 +- compiler/base/hierarchy_design.py | 10 +- compiler/base/hierarchy_layout.py | 343 +++++++++++++++--- compiler/base/hierarchy_spice.py | 12 +- compiler/base/lef.py | 4 +- .../{characterizer => base}/logical_effort.py | 4 +- compiler/base/pin_layout.py | 2 +- compiler/base/route.py | 8 +- compiler/base/utils.py | 6 +- compiler/{router => base}/vector3d.py | 0 compiler/base/wire.py | 18 +- compiler/base/wire_path.py | 6 +- compiler/characterizer/simulation.py | 4 +- compiler/datasheet/__init__.py | 1 + compiler/datasheet/datasheet.py | 2 +- compiler/datasheet/datasheet_gen.py | 18 +- compiler/datasheet/table_gen.py | 2 + compiler/drc/__init__.py | 6 + .../{base => drc}/custom_cell_properties.py | 0 .../{base => drc}/custom_layer_properties.py | 0 compiler/drc/design_rules.py | 4 +- compiler/{modules => drc}/module_type.py | 0 compiler/globals.py | 24 +- compiler/modules/__init__.py | 82 +++++ compiler/modules/and2_dec.py | 8 +- compiler/modules/and3_dec.py | 8 +- compiler/modules/and4_dec.py | 8 +- compiler/modules/bank.py | 6 +- compiler/modules/bank_select.py | 17 +- .../{bitcells => modules}/bitcell_1port.py | 4 +- .../{bitcells => modules}/bitcell_2port.py | 6 +- compiler/modules/bitcell_array.py | 2 +- .../{bitcells => modules}/bitcell_base.py | 22 +- compiler/modules/bitcell_base_array.py | 4 +- compiler/modules/col_cap_array.py | 2 +- .../col_cap_bitcell_1port.py | 4 +- .../col_cap_bitcell_2port.py | 4 +- compiler/modules/column_decoder.py | 6 +- compiler/{pgates => modules}/column_mux.py | 7 +- compiler/modules/column_mux_array.py | 6 +- compiler/modules/control_logic.py | 10 +- compiler/modules/delay_chain.py | 6 +- compiler/{custom => modules}/dff.py | 4 +- compiler/modules/dff_array.py | 6 +- compiler/modules/dff_buf.py | 6 +- compiler/modules/dff_buf_array.py | 6 +- compiler/modules/dff_inv.py | 6 +- compiler/modules/dff_inv_array.py | 6 +- compiler/modules/dummy_array.py | 2 +- .../dummy_bitcell_1port.py | 4 +- .../dummy_bitcell_2port.py | 4 +- .../{bitcells => modules}/dummy_pbitcell.py | 8 +- compiler/modules/global_bitcell_array.py | 6 +- compiler/modules/hierarchical_decoder.py | 6 +- compiler/modules/hierarchical_predecode.py | 6 +- compiler/modules/hierarchical_predecode2x4.py | 2 +- compiler/modules/hierarchical_predecode3x8.py | 2 +- .../modules/hierarchical_predecode4x16.py | 2 +- compiler/{custom => modules}/inv_dec.py | 18 +- compiler/modules/local_bitcell_array.py | 6 +- compiler/modules/multibank.py | 11 +- compiler/{custom => modules}/nand2_dec.py | 20 +- compiler/{custom => modules}/nand3_dec.py | 20 +- compiler/{custom => modules}/nand4_dec.py | 20 +- compiler/modules/orig_bitcell_array.py | 2 +- compiler/{pgates => modules}/pand2.py | 6 +- compiler/{pgates => modules}/pand3.py | 6 +- compiler/{pgates => modules}/pand4.py | 6 +- compiler/{bitcells => modules}/pbitcell.py | 63 ++-- compiler/{pgates => modules}/pbuf.py | 6 +- compiler/{pgates => modules}/pbuf_dec.py | 8 +- compiler/{pgates => modules}/pdriver.py | 6 +- compiler/{pgates => modules}/pgate.py | 17 +- compiler/{pgates => modules}/pinv.py | 33 +- compiler/{pgates => modules}/pinv_dec.py | 27 +- compiler/{pgates => modules}/pinvbuf.py | 6 +- compiler/{pgates => modules}/pnand2.py | 31 +- compiler/{pgates => modules}/pnand3.py | 27 +- compiler/{pgates => modules}/pnand4.py | 27 +- compiler/{pgates => modules}/pnor2.py | 6 +- compiler/modules/port_address.py | 6 +- compiler/modules/port_data.py | 6 +- compiler/{pgates => modules}/precharge.py | 15 +- compiler/modules/precharge_array.py | 6 +- compiler/{pgates => modules}/ptristate_inv.py | 27 +- compiler/{pgates => modules}/ptx.py | 23 +- compiler/{pgates => modules}/pwrite_driver.py | 6 +- .../replica_bitcell_1port.py | 10 +- .../replica_bitcell_2port.py | 10 +- compiler/modules/replica_bitcell_array.py | 9 +- compiler/modules/replica_column.py | 4 +- .../{bitcells => modules}/replica_pbitcell.py | 8 +- compiler/modules/row_cap_array.py | 2 +- .../row_cap_bitcell_1port.py | 4 +- .../row_cap_bitcell_2port.py | 4 +- compiler/{custom => modules}/sense_amp.py | 8 +- compiler/modules/sense_amp_array.py | 6 +- compiler/{sram => modules}/sram.py | 13 +- compiler/{sram => modules}/sram_1bank.py | 11 +- compiler/{sram => modules}/sram_2bank.py | 10 +- compiler/{sram => modules}/sram_base.py | 20 +- compiler/{sram => modules}/sram_config.py | 0 compiler/{custom => modules}/tri_gate.py | 4 +- compiler/modules/tri_gate_array.py | 6 +- compiler/modules/wordline_buffer_array.py | 8 +- .../{pgates => modules}/wordline_driver.py | 6 +- compiler/modules/wordline_driver_array.py | 6 +- compiler/{custom => modules}/write_driver.py | 4 +- compiler/modules/write_driver_array.py | 6 +- compiler/modules/write_mask_and_array.py | 6 +- compiler/openram.py | 4 +- compiler/router/__init__.py | 5 + compiler/router/direction.py | 2 +- compiler/router/grid.py | 4 +- compiler/router/grid_path.py | 6 +- compiler/router/grid_utils.py | 4 +- compiler/router/pin_group.py | 8 +- compiler/router/router.py | 20 +- compiler/router/router_tech.py | 4 +- compiler/router/signal_escape_router.py | 6 +- compiler/router/signal_grid.py | 7 +- compiler/router/supply_grid.py | 4 +- compiler/router/supply_grid_router.py | 12 +- compiler/router/supply_tree_router.py | 10 +- compiler/sram/__init__.py | 5 + compiler/sram_factory.py | 15 +- compiler/tests/00_code_format_check_test.py | 2 +- compiler/tests/01_library_test.py | 2 +- compiler/tests/03_contact_test.py | 2 +- compiler/tests/03_path_test.py | 22 +- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 2 +- compiler/tests/03_ptx_4finger_nmos_test.py | 2 +- compiler/tests/03_ptx_4finger_pmos_test.py | 2 +- compiler/tests/03_ptx_no_contacts_test.py | 2 +- compiler/tests/03_wire_test.py | 10 +- compiler/tests/04_and2_dec_test.py | 2 +- compiler/tests/04_and3_dec_test.py | 2 +- compiler/tests/04_and4_dec_test.py | 2 +- compiler/tests/04_column_mux_1rw_1r_test.py | 2 +- compiler/tests/04_column_mux_pbitcell_test.py | 2 +- compiler/tests/04_column_mux_test.py | 2 +- compiler/tests/04_dff_buf_test.py | 2 +- compiler/tests/04_dummy_pbitcell_test.py | 8 +- compiler/tests/04_pand2_test.py | 6 +- compiler/tests/04_pand3_test.py | 6 +- compiler/tests/04_pand4_test.py | 6 +- compiler/tests/04_pbitcell_test.py | 2 +- compiler/tests/04_pbuf_dec_8x_test.py | 2 +- compiler/tests/04_pbuf_test.py | 2 +- compiler/tests/04_pdriver_test.py | 2 +- compiler/tests/04_pinv_100x_test.py | 2 +- compiler/tests/04_pinv_10x_test.py | 2 +- compiler/tests/04_pinv_1x_beta_test.py | 2 +- compiler/tests/04_pinv_1x_test.py | 2 +- compiler/tests/04_pinv_2x_test.py | 2 +- compiler/tests/04_pinv_dec_1x_test.py | 2 +- compiler/tests/04_pinvbuf_test.py | 2 +- compiler/tests/04_pnand2_test.py | 2 +- compiler/tests/04_pnand3_test.py | 2 +- compiler/tests/04_pnand4_test.py | 2 +- compiler/tests/04_pnor2_test.py | 2 +- compiler/tests/04_precharge_1rw_1r_test.py | 2 +- compiler/tests/04_precharge_pbitcell_test.py | 2 +- compiler/tests/04_precharge_test.py | 2 +- compiler/tests/04_pwrite_driver_test.py | 2 +- compiler/tests/04_replica_pbitcell_test.py | 8 +- compiler/tests/04_wordline_driver_test.py | 2 +- .../tests/05_bitcell_array_1rw_1r_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/05_dummy_array_test.py | 2 +- compiler/tests/05_pbitcell_array_test.py | 2 +- .../tests/06_column_decoder_16row_test.py | 2 +- ...hierarchical_decoder_132row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_132row_test.py | 2 +- ..._hierarchical_decoder_16row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_16row_test.py | 2 +- ..._hierarchical_decoder_17row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_17row_test.py | 2 +- ..._hierarchical_decoder_32row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_32row_test.py | 2 +- ...ierarchical_decoder_4096row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_4096row_test.py | 2 +- ...hierarchical_decoder_512row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_512row_test.py | 2 +- ..._hierarchical_decoder_64row_1rw_1r_test.py | 2 +- .../06_hierarchical_decoder_64row_test.py | 2 +- .../06_hierarchical_decoder_pbitcell_test.py | 2 +- ...6_hierarchical_predecode2x4_1rw_1r_test.py | 2 +- ...hierarchical_predecode2x4_pbitcell_test.py | 2 +- .../06_hierarchical_predecode2x4_test.py | 2 +- ...6_hierarchical_predecode3x8_1rw_1r_test.py | 2 +- ...hierarchical_predecode3x8_pbitcell_test.py | 2 +- .../06_hierarchical_predecode3x8_test.py | 2 +- .../06_hierarchical_predecode4x16_test.py | 2 +- .../07_column_mux_array_16mux_1rw_1r_test.py | 2 +- .../tests/07_column_mux_array_16mux_test.py | 2 +- .../07_column_mux_array_2mux_1rw_1r_test.py | 2 +- .../tests/07_column_mux_array_2mux_test.py | 2 +- .../07_column_mux_array_4mux_1rw_1r_test.py | 2 +- .../tests/07_column_mux_array_4mux_test.py | 2 +- .../07_column_mux_array_8mux_1rw_1r_test.py | 2 +- .../tests/07_column_mux_array_8mux_test.py | 2 +- .../07_column_mux_array_pbitcell_test.py | 2 +- .../tests/08_precharge_array_1rw_1r_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- .../tests/08_wordline_buffer_array_test.py | 2 +- .../08_wordline_driver_array_1rw_1r_test.py | 2 +- .../08_wordline_driver_array_pbitcell_test.py | 2 +- .../tests/08_wordline_driver_array_test.py | 2 +- .../tests/09_sense_amp_array_1rw_1r_test.py | 2 +- .../tests/09_sense_amp_array_pbitcell_test.py | 2 +- .../09_sense_amp_array_spare_cols_test.py | 2 +- compiler/tests/09_sense_amp_array_test.py | 2 +- .../10_write_driver_array_1rw_1r_test.py | 2 +- .../10_write_driver_array_pbitcell_test.py | 2 +- .../10_write_driver_array_spare_cols_test.py | 2 +- compiler/tests/10_write_driver_array_test.py | 2 +- ..._write_driver_array_wmask_pbitcell_test.py | 2 +- ...rite_driver_array_wmask_spare_cols_test.py | 2 +- .../tests/10_write_driver_array_wmask_test.py | 2 +- .../10_write_mask_and_array_1rw_1r_test.py | 2 +- .../10_write_mask_and_array_pbitcell_test.py | 2 +- .../tests/10_write_mask_and_array_test.py | 2 +- compiler/tests/11_dff_array_test.py | 2 +- compiler/tests/11_dff_buf_array_test.py | 2 +- compiler/tests/12_tri_gate_array_test.py | 2 +- compiler/tests/13_delay_chain_test.py | 2 +- ...plica_bitcell_array_bothrbl_1rw_1r_test.py | 2 +- ...plica_bitcell_array_leftrbl_1rw_1r_test.py | 2 +- ...replica_bitcell_array_norbl_1rw_1r_test.py | 2 +- .../tests/14_replica_bitcell_array_test.py | 2 +- .../tests/14_replica_column_1rw_1r_test.py | 2 +- compiler/tests/14_replica_column_test.py | 2 +- .../tests/14_replica_pbitcell_array_test.py | 2 +- .../15_global_bitcell_array_1rw_1r_test.py | 2 +- .../tests/15_global_bitcell_array_test.py | 2 +- .../15_local_bitcell_array_1rw_1r_test.py | 2 +- compiler/tests/15_local_bitcell_array_test.py | 2 +- .../tests/16_control_logic_multiport_test.py | 4 +- compiler/tests/16_control_logic_r_test.py | 2 +- compiler/tests/16_control_logic_rw_test.py | 2 +- compiler/tests/16_control_logic_w_test.py | 2 +- .../18_port_address_16rows_1rw_1r_test.py | 2 +- compiler/tests/18_port_address_16rows_test.py | 2 +- .../18_port_address_256rows_1rw_1r_test.py | 2 +- .../tests/18_port_address_512rows_test.py | 2 +- .../tests/18_port_data_16mux_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_16mux_test.py | 4 +- .../tests/18_port_data_2mux_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_2mux_test.py | 4 +- .../tests/18_port_data_4mux_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_4mux_test.py | 4 +- .../tests/18_port_data_8mux_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_8mux_test.py | 4 +- .../tests/18_port_data_nomux_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_nomux_test.py | 4 +- .../tests/18_port_data_spare_cols_test.py | 4 +- .../tests/18_port_data_wmask_1rw_1r_test.py | 4 +- compiler/tests/18_port_data_wmask_test.py | 4 +- .../tests/19_bank_select_pbitcell_test.py | 48 --- compiler/tests/19_bank_select_test.py | 35 -- compiler/tests/19_multi_bank_test.py | 4 +- compiler/tests/19_pmulti_bank_test.py | 4 +- compiler/tests/19_psingle_bank_test.py | 4 +- .../tests/19_single_bank_16mux_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_16mux_test.py | 4 +- compiler/tests/19_single_bank_1w_1r_test.py | 4 +- .../tests/19_single_bank_2mux_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_2mux_test.py | 4 +- .../tests/19_single_bank_4mux_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_4mux_test.py | 4 +- .../tests/19_single_bank_8mux_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_8mux_test.py | 4 +- .../19_single_bank_global_bitline_test.py | 4 +- .../tests/19_single_bank_nomux_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_nomux_test.py | 4 +- .../tests/19_single_bank_spare_cols_test.py | 4 +- .../tests/19_single_bank_wmask_1rw_1r_test.py | 4 +- compiler/tests/19_single_bank_wmask_test.py | 4 +- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 4 +- .../20_psram_1bank_2mux_1rw_1w_wmask_test.py | 4 +- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 4 +- compiler/tests/20_psram_1bank_2mux_test.py | 4 +- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 4 +- .../tests/20_sram_1bank_16mux_1rw_1r_test.py | 4 +- compiler/tests/20_sram_1bank_16mux_test.py | 4 +- ..._sram_1bank_2mux_1rw_1r_spare_cols_test.py | 4 +- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 4 +- ...0_sram_1bank_2mux_1w_1r_spare_cols_test.py | 4 +- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 4 +- .../tests/20_sram_1bank_2mux_global_test.py | 4 +- compiler/tests/20_sram_1bank_2mux_test.py | 4 +- ...0_sram_1bank_2mux_wmask_spare_cols_test.py | 4 +- .../tests/20_sram_1bank_2mux_wmask_test.py | 4 +- .../20_sram_1bank_32b_1024_wmask_test.py | 4 +- .../tests/20_sram_1bank_4mux_1rw_1r_test.py | 4 +- compiler/tests/20_sram_1bank_4mux_test.py | 4 +- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 4 +- compiler/tests/20_sram_1bank_8mux_test.py | 4 +- ...sram_1bank_nomux_1rw_1r_spare_cols_test.py | 4 +- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 4 +- .../20_sram_1bank_nomux_spare_cols_test.py | 4 +- compiler/tests/20_sram_1bank_nomux_test.py | 3 +- ...0_sram_1bank_nomux_wmask_sparecols_test.py | 4 +- .../tests/20_sram_1bank_nomux_wmask_test.py | 4 +- compiler/tests/20_sram_1bank_ring_test.py | 4 +- compiler/tests/20_sram_2bank_test.py | 4 +- compiler/tests/21_hspice_delay_test.py | 4 +- compiler/tests/21_hspice_setuphold_test.py | 2 +- compiler/tests/21_model_delay_test.py | 6 +- .../tests/21_ngspice_delay_extra_rows_test.py | 4 +- .../tests/21_ngspice_delay_global_test.py | 4 +- compiler/tests/21_ngspice_delay_test.py | 4 +- compiler/tests/21_ngspice_setuphold_test.py | 2 +- compiler/tests/21_regression_delay_test.py | 6 +- compiler/tests/21_xyce_delay_test.py | 4 +- compiler/tests/21_xyce_setuphold_test.py | 2 +- .../tests/22_psram_1bank_2mux_func_test.py | 4 +- .../tests/22_psram_1bank_4mux_func_test.py | 4 +- .../tests/22_psram_1bank_8mux_func_test.py | 4 +- .../tests/22_psram_1bank_nomux_func_test.py | 4 +- .../tests/22_sram_1bank_2mux_func_test.py | 4 +- .../22_sram_1bank_2mux_global_func_test.py | 4 +- .../22_sram_1bank_2mux_sparecols_func_test.py | 4 +- .../tests/22_sram_1bank_4mux_func_test.py | 4 +- .../tests/22_sram_1bank_8mux_func_test.py | 4 +- .../22_sram_1bank_nomux_1rw_1r_func_test.py | 4 +- .../tests/22_sram_1bank_nomux_func_test.py | 4 +- ...22_sram_1bank_nomux_sparecols_func_test.py | 4 +- .../22_sram_1bank_wmask_1rw_1r_func_test.py | 4 +- compiler/tests/22_sram_wmask_func_test.py | 4 +- .../23_lib_sram_linear_regression_test.py | 6 +- .../tests/23_lib_sram_model_corners_test.py | 6 +- compiler/tests/23_lib_sram_model_test.py | 6 +- compiler/tests/23_lib_sram_prune_test.py | 6 +- compiler/tests/23_lib_sram_test.py | 6 +- compiler/tests/24_lef_sram_test.py | 6 +- compiler/tests/25_verilog_sram_test.py | 6 +- compiler/tests/26_hspice_pex_pinv_test.py | 2 +- compiler/tests/26_ngspice_pex_pinv_test.py | 2 +- compiler/tests/26_sram_pex_test.py | 4 +- compiler/tests/30_openram_back_end_test.py | 2 +- compiler/tests/30_openram_front_end_test.py | 2 +- compiler/tests/50_riscv_1k_1rw1r_func_test.py | 4 +- compiler/tests/50_riscv_1k_1rw_func_test.py | 4 +- compiler/tests/50_riscv_1rw1r_func_test.py | 4 +- compiler/tests/50_riscv_1rw1r_phys_test.py | 4 +- compiler/tests/50_riscv_1rw_func_test.py | 4 +- compiler/tests/50_riscv_1rw_phys_test.py | 4 +- compiler/tests/50_riscv_2k_1rw1r_func_test.py | 4 +- compiler/tests/50_riscv_2k_1rw_func_test.py | 4 +- compiler/tests/50_riscv_4k_1rw1r_func_test.py | 4 +- compiler/tests/50_riscv_4k_1rw_func_test.py | 4 +- .../tests/50_riscv_512b_1rw1r_func_test.py | 4 +- compiler/tests/50_riscv_512b_1rw_func_test.py | 4 +- compiler/tests/50_riscv_8k_1rw1r_func_test.py | 4 +- compiler/tests/50_riscv_8k_1rw_func_test.py | 4 +- compiler/tests/testutils.py | 5 +- compiler/verify/calibre.py | 4 +- compiler/verify/klayout.py | 2 +- compiler/verify/magic.py | 4 +- openram.mk | 2 + technology/freepdk45/tech/tech.py | 21 +- technology/scn4m_subm/tech/tech.py | 17 +- technology/sky130/custom/__init__.py | 0 .../{modules => custom}/sky130_bitcell.py | 4 +- .../sky130_bitcell_array.py | 4 +- .../sky130_bitcell_base_array.py | 4 +- .../{modules => custom}/sky130_col_cap.py | 4 +- .../sky130_col_cap_array.py | 4 +- .../{modules => custom}/sky130_corner.py | 16 +- .../{modules => custom}/sky130_dummy_array.py | 4 +- .../sky130_dummy_bitcell.py | 4 +- .../{modules => custom}/sky130_internal.py | 16 +- .../sky130_replica_bitcell.py | 8 +- .../sky130_replica_bitcell_array.py | 8 +- .../sky130_replica_column.py | 4 +- .../{modules => custom}/sky130_row_cap.py | 4 +- .../sky130_row_cap_array.py | 2 +- technology/sky130/tech/tech.py | 22 +- 388 files changed, 1450 insertions(+), 1391 deletions(-) create mode 100644 compiler/base/__init__.py rename compiler/{characterizer => base}/logical_effort.py (97%) rename compiler/{router => base}/vector3d.py (100%) create mode 100644 compiler/datasheet/__init__.py create mode 100644 compiler/drc/__init__.py rename compiler/{base => drc}/custom_cell_properties.py (100%) rename compiler/{base => drc}/custom_layer_properties.py (100%) rename compiler/{modules => drc}/module_type.py (100%) create mode 100644 compiler/modules/__init__.py rename compiler/{bitcells => modules}/bitcell_1port.py (93%) rename compiler/{bitcells => modules}/bitcell_2port.py (97%) rename compiler/{bitcells => modules}/bitcell_base.py (95%) rename compiler/{bitcells => modules}/col_cap_bitcell_1port.py (88%) rename compiler/{bitcells => modules}/col_cap_bitcell_2port.py (88%) rename compiler/{pgates => modules}/column_mux.py (99%) rename compiler/{custom => modules}/dff.py (96%) rename compiler/{bitcells => modules}/dummy_bitcell_1port.py (89%) rename compiler/{bitcells => modules}/dummy_bitcell_2port.py (89%) rename compiler/{bitcells => modules}/dummy_pbitcell.py (96%) rename compiler/{custom => modules}/inv_dec.py (82%) rename compiler/{custom => modules}/nand2_dec.py (87%) rename compiler/{custom => modules}/nand3_dec.py (87%) rename compiler/{custom => modules}/nand4_dec.py (87%) rename compiler/{pgates => modules}/pand2.py (98%) rename compiler/{pgates => modules}/pand3.py (98%) rename compiler/{pgates => modules}/pand4.py (98%) rename compiler/{bitcells => modules}/pbitcell.py (96%) rename compiler/{pgates => modules}/pbuf.py (98%) rename compiler/{pgates => modules}/pbuf_dec.py (96%) rename compiler/{pgates => modules}/pdriver.py (98%) rename compiler/{pgates => modules}/pgate.py (98%) rename compiler/{pgates => modules}/pinv.py (94%) rename compiler/{pgates => modules}/pinv_dec.py (92%) rename compiler/{pgates => modules}/pinvbuf.py (99%) rename compiler/{pgates => modules}/pnand2.py (94%) rename compiler/{pgates => modules}/pnand3.py (96%) rename compiler/{pgates => modules}/pnand4.py (96%) rename compiler/{pgates => modules}/pnor2.py (99%) rename compiler/{pgates => modules}/precharge.py (96%) rename compiler/{pgates => modules}/ptristate_inv.py (89%) rename compiler/{pgates => modules}/ptx.py (97%) rename compiler/{pgates => modules}/pwrite_driver.py (99%) rename compiler/{bitcells => modules}/replica_bitcell_1port.py (89%) rename compiler/{bitcells => modules}/replica_bitcell_2port.py (90%) rename compiler/{bitcells => modules}/replica_pbitcell.py (95%) rename compiler/{bitcells => modules}/row_cap_bitcell_1port.py (87%) rename compiler/{bitcells => modules}/row_cap_bitcell_2port.py (87%) rename compiler/{custom => modules}/sense_amp.py (96%) rename compiler/{sram => modules}/sram.py (95%) rename compiler/{sram => modules}/sram_1bank.py (99%) rename compiler/{sram => modules}/sram_2bank.py (98%) rename compiler/{sram => modules}/sram_base.py (98%) rename compiler/{sram => modules}/sram_config.py (100%) rename compiler/{custom => modules}/tri_gate.py (96%) rename compiler/{pgates => modules}/wordline_driver.py (98%) rename compiler/{custom => modules}/write_driver.py (96%) create mode 100644 compiler/router/__init__.py create mode 100644 compiler/sram/__init__.py delete mode 100755 compiler/tests/19_bank_select_pbitcell_test.py delete mode 100755 compiler/tests/19_bank_select_test.py create mode 100644 technology/sky130/custom/__init__.py rename technology/sky130/{modules => custom}/sky130_bitcell.py (94%) rename technology/sky130/{modules => custom}/sky130_bitcell_array.py (97%) rename technology/sky130/{modules => custom}/sky130_bitcell_base_array.py (99%) rename technology/sky130/{modules => custom}/sky130_col_cap.py (96%) rename technology/sky130/{modules => custom}/sky130_col_cap_array.py (99%) rename technology/sky130/{modules => custom}/sky130_corner.py (63%) rename technology/sky130/{modules => custom}/sky130_dummy_array.py (98%) rename technology/sky130/{modules => custom}/sky130_dummy_bitcell.py (91%) rename technology/sky130/{modules => custom}/sky130_internal.py (64%) rename technology/sky130/{modules => custom}/sky130_replica_bitcell.py (90%) rename technology/sky130/{modules => custom}/sky130_replica_bitcell_array.py (99%) rename technology/sky130/{modules => custom}/sky130_replica_column.py (99%) rename technology/sky130/{modules => custom}/sky130_row_cap.py (93%) rename technology/sky130/{modules => custom}/sky130_row_cap_array.py (98%) diff --git a/README.md b/README.md index 4a3ec69a..438c33db 100644 --- a/README.md +++ b/README.md @@ -26,28 +26,33 @@ things that need to be fixed. # Basic Setup -## Docker - -We have a [docker setup](./docker) to run OpenRAM. - ## Dependencies -The OpenRAM compiler has very few dependencies: -+ [Ngspice] 34 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) or [Xyce] 7.4 (or later) +Please see the Dockerfile for the required versions of tools. + +In general, the OpenRAM compiler has very few dependencies: ++ Docker ++ Make + Python 3.6 or higher + Various Python packages (pip install -r requirements.txt) + [Git] -If you want to perform DRC and LVS, you will need either: -+ Calibre (for [FreePDK45]) -+ [Magic] 8.3.197 or newer -+ [Netgen] 1.5.195 or newer +## Docker + +We have a [docker setup](./docker) to run OpenRAM. To use this, you should run: +``` +cd openram/docker +make build +``` +This must be run once and will take a while to build all the tools. + + +## Environment You must set two environment variables: + OPENRAM\_HOME should point to the compiler source directory. + OPENERAM\_TECH should point to one or more root technology directories (colon separated). -## Environment For example add this to your .bashrc: @@ -56,17 +61,23 @@ For example add this to your .bashrc: export OPENRAM_TECH="$HOME/openram/technology" ``` -You may also wish to add OPENRAM\_HOME to your PYTHONPATH: +You should also add OPENRAM\_HOME to your PYTHONPATH: ``` - export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME" + export PYTHONPATH=$OPENRAM_HOME +``` +Note that if you want symbols to resolve in your editor, you may also want to add the specific technology +directory that you use and any custom technology modules as well. For example: +``` + export PYTHONPATH="$OPENRAM_HOME:$OPENRAM_TECH/sky130:$OPENRAM_TECH/sky130/custom" +``` We include the tech files necessary for [SCMOS] SCN4M_SUBM, [FreePDK45]. The [SCMOS] spice models, however, are generic and should be replaced with foundry models. You may get the entire [FreePDK45 PDK here][FreePDK45]. -``` + ### Sky130 Setup To install [Sky130], you must have the open_pdks files installed in $PDK_ROOT. @@ -80,7 +91,7 @@ by running: cd $HOME/openram make install -``` + # Basic Usage Once you have defined the environment, you can run OpenRAM from the command line @@ -88,7 +99,7 @@ using a single configuration file written in Python. For example, create a file called *myconfig.py* specifying the following parameters for your memory: - +``` # Data word size word_size = 2 # Number of words in the memory @@ -142,9 +153,9 @@ make -j 3 ``` The -j can run with 3 threads. By default, this will run in all technologies. -To run a specific test: +To run a specific test in all technologies: ``` -ce openram/compiler/tests +cd openram/compiler/tests make 05_bitcell_array_test ``` To run a specific technology: @@ -159,6 +170,14 @@ pass it as an argument to OpenRAM: ARGS="-v" make 05_bitcell_array_test ``` +Unit test results are put in a directory: +``` +openram/compiler/tests/results// +``` +If the test fails, there will be a tmp directory with intermediate results. +If the test passes, this directory will be deleted to save space. +You can view the .out file to see what the output of a test is in either case. + # Get Involved + [Port it](./PORTING.md) to a new technology. @@ -207,6 +226,7 @@ If I forgot to add you, please let me know! [dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu [user-group-subscribe]: mailto:openram-user-group+subscribe@ucsc.edu +[Klayout]: https://www.klayout.de/ [Magic]: http://opencircuitdesign.com/magic/ [Netgen]: http://opencircuitdesign.com/netgen/ [Qflow]: http://opencircuitdesign.com/qflow/history.html diff --git a/compiler/base/__init__.py b/compiler/base/__init__.py new file mode 100644 index 00000000..25f44cf7 --- /dev/null +++ b/compiler/base/__init__.py @@ -0,0 +1,21 @@ +from .channel_route import * +from .contact import * +from .delay_data import * +from .design import * +from .errors import * +from .geometry import * +from .hierarchy_design import * +from .hierarchy_layout import * +from .hierarchy_spice import * +from .lef import * +from .logical_effort import * +from .pin_layout import * +from .power_data import * +from .route import * +from .timing_graph import * +from .utils import * +from .vector import * +from .verilog import * +from .wire_path import * +from .wire import * +from .wire_spice_model import * diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index d64b7e3c..7cd1fb53 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -8,8 +8,8 @@ import collections import debug from tech import drc -from vector import vector -import design +from .vector import vector +from .design import design class channel_net(): @@ -75,7 +75,7 @@ class channel_net(): return min_overlap or max_overlap -class channel_route(design.design): +class channel_route(design): unique_id = 0 diff --git a/compiler/base/contact.py b/compiler/base/contact.py index bb6eb391..5f2f41d0 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -5,16 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import hierarchy_design import debug -from tech import drc, layer -import tech -from vector import vector -from sram_factory import factory -import sys +from .hierarchy_design import hierarchy_design +from .vector import vector +from tech import drc, layer, preferred_directions +from tech import layer as tech_layers -class contact(hierarchy_design.hierarchy_design): +class contact(hierarchy_design): """ Object for a contact shape with its conductor enclosures. Creates a contact array minimum active or poly enclosure and metal1 @@ -51,20 +49,20 @@ class contact(hierarchy_design.hierarchy_design): # Non-preferred directions if directions == "nonpref": - first_dir = "H" if tech.preferred_directions[layer_stack[0]]=="V" else "V" - second_dir = "H" if tech.preferred_directions[layer_stack[2]]=="V" else "V" + first_dir = "H" if preferred_directions[layer_stack[0]]=="V" else "V" + second_dir = "H" if preferred_directions[layer_stack[2]]=="V" else "V" self.directions = (first_dir, second_dir) # Preferred directions elif directions == "pref": - self.directions = (tech.preferred_directions[layer_stack[0]], - tech.preferred_directions[layer_stack[2]]) + self.directions = (preferred_directions[layer_stack[0]], + preferred_directions[layer_stack[2]]) # User directions elif directions: self.directions = directions # Preferred directions else: - self.directions = (tech.preferred_directions[layer_stack[0]], - tech.preferred_directions[layer_stack[2]]) + self.directions = (preferred_directions[layer_stack[0]], + preferred_directions[layer_stack[2]]) self.offset = vector(0, 0) self.implant_type = implant_type self.well_type = well_type @@ -101,7 +99,7 @@ class contact(hierarchy_design.hierarchy_design): self.second_layer_name = second_layer # Contacts will have unique per first layer - if via_layer in tech.layer: + if via_layer in tech_layers: self.via_layer_name = via_layer elif via_layer == "contact": if first_layer in ("active", "poly"): @@ -194,7 +192,7 @@ class contact(hierarchy_design.hierarchy_design): def create_nitride_cut_enclosure(self): """ Special layer that encloses poly contacts in some processes """ # Check if there is a special poly nitride cut layer - if "npc" not in tech.layer: + if "npc" not in tech_layers: return npc_enclose_poly = drc("npc_enclose_poly") @@ -256,7 +254,7 @@ class contact(hierarchy_design.hierarchy_design): # Optionally implant well if layer exists well_layer = "{}well".format(self.well_type) - if well_layer in tech.layer: + if well_layer in tech_layers: well_width_rule = drc("minwidth_" + well_layer) self.well_enclose_active = drc(well_layer + "_enclose_active") self.well_width = max(self.first_layer_width + 2 * self.well_enclose_active, @@ -275,33 +273,3 @@ class contact(hierarchy_design.hierarchy_design): return self.return_power() -# Set up a static for each layer to be used for measurements -for layer_stack in tech.layer_stacks: - (layer1, via, layer2) = layer_stack - cont = factory.create(module_type="contact", - layer_stack=layer_stack) - module = sys.modules[__name__] - # Also create a contact that is just the first layer - if layer1 == "poly" or layer1 == "active": - setattr(module, layer1 + "_contact", cont) - else: - setattr(module, layer1 + "_via", cont) - -# Set up a static for each well contact for measurements -if "nwell" in tech.layer: - cont = factory.create(module_type="contact", - layer_stack=tech.active_stack, - implant_type="n", - well_type="n") - module = sys.modules[__name__] - setattr(module, "nwell_contact", cont) - -if "pwell" in tech.layer: - cont = factory.create(module_type="contact", - layer_stack=tech.active_stack, - implant_type="p", - well_type="p") - module = sys.modules[__name__] - setattr(module, "pwell_contact", cont) - - diff --git a/compiler/base/design.py b/compiler/base/design.py index f8ca0cb1..ccd9cec1 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -5,15 +5,13 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from hierarchy_design import hierarchy_design -import utils -import contact +import debug from tech import GDS, layer from tech import preferred_directions from tech import cell_properties as props from globals import OPTS -import re -import debug +from . import utils +from .hierarchy_design import hierarchy_design class design(hierarchy_design): @@ -82,201 +80,6 @@ class design(hierarchy_design): for pin in pins: print(pin_name, pin) - @classmethod - def setup_drc_constants(design): - """ - These are some DRC constants used in many places - in the compiler. - """ - # Make some local rules for convenience - from tech import drc - for rule in drc.keys(): - # Single layer width rules - match = re.search(r"minwidth_(.*)", rule) - if match: - if match.group(1) == "active_contact": - setattr(design, "contact_width", drc(match.group(0))) - else: - setattr(design, match.group(1) + "_width", drc(match.group(0))) - - # Single layer area rules - match = re.search(r"minarea_(.*)", rule) - if match: - setattr(design, match.group(0), drc(match.group(0))) - - # Single layer spacing rules - match = re.search(r"(.*)_to_(.*)", rule) - if match and match.group(1) == match.group(2): - setattr(design, match.group(1) + "_space", drc(match.group(0))) - elif match and match.group(1) != match.group(2): - if match.group(2) == "poly_active": - setattr(design, match.group(1) + "_to_contact", - drc(match.group(0))) - else: - setattr(design, match.group(0), drc(match.group(0))) - - match = re.search(r"(.*)_enclose_(.*)", rule) - if match: - setattr(design, match.group(0), drc(match.group(0))) - - match = re.search(r"(.*)_extend_(.*)", rule) - if match: - setattr(design, match.group(0), drc(match.group(0))) - - # Create the maximum well extend active that gets used - # by cells to extend the wells for interaction with other cells - from tech import layer - design.well_extend_active = 0 - if "nwell" in layer: - design.well_extend_active = max(design.well_extend_active, design.nwell_extend_active) - if "pwell" in layer: - design.well_extend_active = max(design.well_extend_active, design.pwell_extend_active) - - # The active offset is due to the well extension - if "pwell" in layer: - design.pwell_enclose_active = drc("pwell_enclose_active") - else: - design.pwell_enclose_active = 0 - if "nwell" in layer: - design.nwell_enclose_active = drc("nwell_enclose_active") - else: - design.nwell_enclose_active = 0 - # Use the max of either so that the poly gates will align properly - design.well_enclose_active = max(design.pwell_enclose_active, - design.nwell_enclose_active, - design.active_space) - - # These are for debugging previous manual rules - if False: - print("poly_width", design.poly_width) - print("poly_space", design.poly_space) - print("m1_width", design.m1_width) - print("m1_space", design.m1_space) - print("m2_width", design.m2_width) - print("m2_space", design.m2_space) - print("m3_width", design.m3_width) - print("m3_space", design.m3_space) - print("m4_width", design.m4_width) - print("m4_space", design.m4_space) - print("active_width", design.active_width) - print("active_space", design.active_space) - print("contact_width", design.contact_width) - print("poly_to_active", design.poly_to_active) - print("poly_extend_active", design.poly_extend_active) - print("poly_to_contact", design.poly_to_contact) - print("active_contact_to_gate", design.active_contact_to_gate) - print("poly_contact_to_gate", design.poly_contact_to_gate) - print("well_enclose_active", design.well_enclose_active) - print("implant_enclose_active", design.implant_enclose_active) - print("implant_space", design.implant_space) - import sys - sys.exit(1) - - @classmethod - def setup_layer_constants(design): - """ - These are some layer constants used - in many places in the compiler. - """ - - from tech import layer_indices - import tech - for layer_id in layer_indices: - key = "{}_stack".format(layer_id) - - # Set the stack as a local helper - try: - layer_stack = getattr(tech, key) - setattr(design, key, layer_stack) - except AttributeError: - pass - - # Skip computing the pitch for non-routing layers - if layer_id in ["active", "nwell"]: - continue - - # Add the pitch - setattr(design, - "{}_pitch".format(layer_id), - design.compute_pitch(layer_id, True)) - - # Add the non-preferrd pitch (which has vias in the "wrong" way) - setattr(design, - "{}_nonpref_pitch".format(layer_id), - design.compute_pitch(layer_id, False)) - - if False: - from tech import preferred_directions - print(preferred_directions) - from tech import layer_indices - for name in layer_indices: - if name == "active": - continue - try: - print("{0} width {1} space {2}".format(name, - getattr(design, "{}_width".format(name)), - getattr(design, "{}_space".format(name)))) - - print("pitch {0} nonpref {1}".format(getattr(design, "{}_pitch".format(name)), - getattr(design, "{}_nonpref_pitch".format(name)))) - except AttributeError: - pass - import sys - sys.exit(1) - - @staticmethod - def compute_pitch(layer, preferred=True): - - """ - This is the preferred direction pitch - i.e. we take the minimum or maximum contact dimension - """ - # Find the layer stacks this is used in - from tech import layer_stacks - pitches = [] - for stack in layer_stacks: - # Compute the pitch with both vias above and below (if they exist) - if stack[0] == layer: - pitches.append(design.compute_layer_pitch(stack, preferred)) - if stack[2] == layer: - pitches.append(design.compute_layer_pitch(stack[::-1], True)) - - return max(pitches) - - @staticmethod - def get_preferred_direction(layer): - return preferred_directions[layer] - - @staticmethod - def compute_layer_pitch(layer_stack, preferred): - - (layer1, via, layer2) = layer_stack - try: - if layer1 == "poly" or layer1 == "active": - contact1 = getattr(contact, layer1 + "_contact") - else: - contact1 = getattr(contact, layer1 + "_via") - except AttributeError: - contact1 = getattr(contact, layer2 + "_via") - - if preferred: - if preferred_directions[layer1] == "V": - contact_width = contact1.first_layer_width - else: - contact_width = contact1.first_layer_height - else: - if preferred_directions[layer1] == "V": - contact_width = contact1.first_layer_height - else: - contact_width = contact1.first_layer_width - layer_space = getattr(design, layer1 + "_space") - - #print(layer_stack) - #print(contact1) - pitch = contact_width + layer_space - - return utils.round_to_grid(pitch) - def setup_multiport_constants(self): """ These are contants and lists that aid multiport design. @@ -324,6 +127,4 @@ class design(hierarchy_design): total_module_power += inst.mod.analytical_power(corner, load) return total_module_power -design.setup_drc_constants() -design.setup_layer_constants() diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index d2f4e98e..3ca87e2e 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -9,13 +9,13 @@ This provides a set of useful generic types for the gdsMill interface. """ import debug -from vector import vector +from .vector import vector import tech import math import copy import numpy as np from globals import OPTS -from utils import round_to_grid +from .utils import round_to_grid class geometry: diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 5e9bec3f..c25864f9 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -5,14 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import hierarchy_layout -import hierarchy_spice +from .hierarchy_layout import layout +from .hierarchy_spice import spice import debug import os from globals import OPTS -class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): +class hierarchy_design(spice, layout): """ Design Class for all modules to inherit the base features. Class consisting of a set of modules and instances of these modules @@ -32,8 +32,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): name = OPTS.output_name + "_" + name cell_name = name - hierarchy_spice.spice.__init__(self, name, cell_name) - hierarchy_layout.layout.__init__(self, name, cell_name) + spice.__init__(self, name, cell_name) + layout.__init__(self, name, cell_name) self.init_graph_params() def get_layout_pins(self, inst): diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 68476a00..fe108c01 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -5,21 +5,26 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import geometry -import gdsMill -import debug -from math import sqrt -from tech import drc, GDS -from tech import layer as techlayer -from tech import layer_indices -from tech import layer_stacks -from tech import preferred_directions import os import sys +import re +from math import sqrt +import debug +from gdsMill import gdsMill +import tech +from tech import drc, GDS +from tech import layer as tech_layer +from tech import layer_indices as tech_layer_indices +from tech import preferred_directions +from tech import layer_stacks as tech_layer_stacks +from tech import active_stack as tech_active_stack +from sram_factory import factory from globals import OPTS -from vector import vector -from pin_layout import pin_layout -from utils import round_to_grid +from .vector import vector +from .pin_layout import pin_layout +from .utils import round_to_grid +from . import geometry + try: from tech import special_purposes except ImportError: @@ -64,11 +69,241 @@ class layout(): self.gds_read() + if "contact" not in self.name: + if not hasattr(layout, "_drc_constants"): + layout._drc_constants = True + layout.setup_drc_constants() + layout.setup_contacts() + layout.setup_layer_constants() + + + @classmethod + def setup_drc_constants(layout): + """ + These are some DRC constants used in many places + in the compiler. + """ + + # Make some local rules for convenience + for rule in drc.keys(): + # Single layer width rules + match = re.search(r"minwidth_(.*)", rule) + if match: + if match.group(1) == "active_contact": + setattr(layout, "contact_width", drc(match.group(0))) + else: + setattr(layout, match.group(1) + "_width", drc(match.group(0))) + + # Single layer area rules + match = re.search(r"minarea_(.*)", rule) + if match: + setattr(layout, match.group(0), drc(match.group(0))) + + # Single layer spacing rules + match = re.search(r"(.*)_to_(.*)", rule) + if match and match.group(1) == match.group(2): + setattr(layout, match.group(1) + "_space", drc(match.group(0))) + elif match and match.group(1) != match.group(2): + if match.group(2) == "poly_active": + setattr(layout, match.group(1) + "_to_contact", + drc(match.group(0))) + else: + setattr(layout, match.group(0), drc(match.group(0))) + + match = re.search(r"(.*)_enclose_(.*)", rule) + if match: + setattr(layout, match.group(0), drc(match.group(0))) + + match = re.search(r"(.*)_extend_(.*)", rule) + if match: + setattr(layout, match.group(0), drc(match.group(0))) + + # Create the maximum well extend active that gets used + # by cells to extend the wells for interaction with other cells + layout.well_extend_active = 0 + if "nwell" in tech_layer: + layout.well_extend_active = max(layout.well_extend_active, layout.nwell_extend_active) + if "pwell" in tech_layer: + layout.well_extend_active = max(layout.well_extend_active, layout.pwell_extend_active) + + # The active offset is due to the well extension + if "pwell" in tech_layer: + layout.pwell_enclose_active = drc("pwell_enclose_active") + else: + layout.pwell_enclose_active = 0 + if "nwell" in tech_layer: + layout.nwell_enclose_active = drc("nwell_enclose_active") + else: + layout.nwell_enclose_active = 0 + # Use the max of either so that the poly gates will align properly + layout.well_enclose_active = max(layout.pwell_enclose_active, + layout.nwell_enclose_active, + layout.active_space) + + # These are for debugging previous manual rules + if False: + print("poly_width", layout.poly_width) + print("poly_space", layout.poly_space) + print("m1_width", layout.m1_width) + print("m1_space", layout.m1_space) + print("m2_width", layout.m2_width) + print("m2_space", layout.m2_space) + print("m3_width", layout.m3_width) + print("m3_space", layout.m3_space) + print("m4_width", layout.m4_width) + print("m4_space", layout.m4_space) + print("active_width", layout.active_width) + print("active_space", layout.active_space) + print("contact_width", layout.contact_width) + print("poly_to_active", layout.poly_to_active) + print("poly_extend_active", layout.poly_extend_active) + print("poly_to_contact", layout.poly_to_contact) + print("active_contact_to_gate", layout.active_contact_to_gate) + print("poly_contact_to_gate", layout.poly_contact_to_gate) + print("well_enclose_active", layout.well_enclose_active) + print("implant_enclose_active", layout.implant_enclose_active) + print("implant_space", layout.implant_space) + import sys + sys.exit(1) + + @classmethod + def setup_layer_constants(layout): + """ + These are some layer constants used + in many places in the compiler. + """ try: from tech import power_grid - self.pwr_grid_layers = [power_grid[0], power_grid[2]] + layout.pwr_grid_layers = [power_grid[0], power_grid[2]] except ImportError: - self.pwr_grid_layers = ["m3", "m4"] + layout.pwr_grid_layers = ["m3", "m4"] + + for layer_id in tech_layer_indices: + key = "{}_stack".format(layer_id) + + # Set the stack as a local helper + try: + layer_stack = getattr(tech, key) + setattr(layout, key, layer_stack) + except AttributeError: + pass + + # Skip computing the pitch for non-routing layers + if layer_id in ["active", "nwell"]: + continue + + # Add the pitch + setattr(layout, + "{}_pitch".format(layer_id), + layout.compute_pitch(layer_id, True)) + + # Add the non-preferrd pitch (which has vias in the "wrong" way) + setattr(layout, + "{}_nonpref_pitch".format(layer_id), + layout.compute_pitch(layer_id, False)) + + if False: + for name in tech_layer_indices: + if name == "active": + continue + try: + print("{0} width {1} space {2}".format(name, + getattr(layout, "{}_width".format(name)), + getattr(layout, "{}_space".format(name)))) + + print("pitch {0} nonpref {1}".format(getattr(layout, "{}_pitch".format(name)), + getattr(layout, "{}_nonpref_pitch".format(name)))) + except AttributeError: + pass + import sys + sys.exit(1) + + @staticmethod + def compute_pitch(layer, preferred=True): + """ + This is the preferred direction pitch + i.e. we take the minimum or maximum contact dimension + """ + # Find the layer stacks this is used in + pitches = [] + for stack in tech_layer_stacks: + # Compute the pitch with both vias above and below (if they exist) + if stack[0] == layer: + pitches.append(layout.compute_layer_pitch(stack, preferred)) + if stack[2] == layer: + pitches.append(layout.compute_layer_pitch(stack[::-1], True)) + + return max(pitches) + + @staticmethod + def get_preferred_direction(layer): + return preferred_directions[layer] + + @staticmethod + def compute_layer_pitch(layer_stack, preferred): + + (layer1, via, layer2) = layer_stack + try: + if layer1 == "poly" or layer1 == "active": + contact1 = getattr(layout, layer1 + "_contact") + else: + contact1 = getattr(layout, layer1 + "_via") + except AttributeError: + contact1 = getattr(layout, layer2 + "_via") + + if preferred: + if preferred_directions[layer1] == "V": + contact_width = contact1.first_layer_width + else: + contact_width = contact1.first_layer_height + else: + if preferred_directions[layer1] == "V": + contact_width = contact1.first_layer_height + else: + contact_width = contact1.first_layer_width + layer_space = getattr(layout, layer1 + "_space") + + #print(layer_stack) + #print(contact1) + pitch = contact_width + layer_space + + return round_to_grid(pitch) + + + @classmethod + def setup_contacts(layout): + # Set up a static for each layer to be used for measurements + # unless we are a contact class! + + for layer_stack in tech_layer_stacks: + (layer1, via, layer2) = layer_stack + cont = factory.create(module_type="contact", + layer_stack=layer_stack) + module = sys.modules[__name__] + # Also create a contact that is just the first layer + if layer1 == "poly" or layer1 == "active": + setattr(layout, layer1 + "_contact", cont) + else: + setattr(layout, layer1 + "_via", cont) + + # Set up a static for each well contact for measurements + if "nwell" in tech_layer: + cont = factory.create(module_type="contact", + layer_stack=tech_active_stack, + implant_type="n", + well_type="n") + module = sys.modules[__name__] + setattr(layout, "nwell_contact", cont) + + if "pwell" in tech_layer: + cont = factory.create(module_type="contact", + layer_stack=tech_active_stack, + implant_type="p", + well_type="p") + module = sys.modules[__name__] + setattr(layout, "pwell_contact", cont) + + ############################################################ # GDS layout @@ -171,7 +406,7 @@ class layout(): this layout on a layer """ # Only consider the layer not the purpose for now - layerNumber = techlayer[layer][0] + layerNumber = tech_layer[layer][0] try: highestx = max(obj.rx() for obj in self.objs if obj.layerNumber == layerNumber) except ValueError: @@ -195,7 +430,7 @@ class layout(): this layout on a layer """ # Only consider the layer not the purpose for now - layerNumber = techlayer[layer][0] + layerNumber = tech_layer[layer][0] try: lowestx = min(obj.lx() for obj in self.objs if obj.layerNumber == layerNumber) except ValueError: @@ -273,7 +508,7 @@ class layout(): width = drc["minwidth_{}".format(layer)] if not height: height = drc["minwidth_{}".format(layer)] - lpp = techlayer[layer] + lpp = tech_layer[layer] self.objs.append(geometry.rectangle(lpp, offset, width, @@ -289,7 +524,7 @@ class layout(): width = drc["minwidth_{}".format(layer)] if not height: height = drc["minwidth_{}".format(layer)] - lpp = techlayer[layer] + lpp = tech_layer[layer] corrected_offset = offset - vector(0.5 * width, 0.5 * height) self.objs.append(geometry.rectangle(lpp, corrected_offset, @@ -599,10 +834,10 @@ class layout(): def get_metal_layers(self, from_layer, to_layer): - from_id = layer_indices[from_layer] - to_id = layer_indices[to_layer] + from_id = tech_layer_indices[from_layer] + to_id = tech_layer_indices[to_layer] - layer_list = [x for x in layer_indices.keys() if layer_indices[x] >= from_id and layer_indices[x] < to_id] + layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] >= from_id and tech_layer_indices[x] < to_id] return layer_list @@ -938,22 +1173,22 @@ class layout(): def add_label(self, text, layer, offset=[0, 0], zoom=None): """Adds a text label on the given layer,offset, and zoom level""" debug.info(5, "add label " + str(text) + " " + layer + " " + str(offset)) - lpp = techlayer[layer] + lpp = tech_layer[layer] self.objs.append(geometry.label(text, lpp, offset, zoom)) return self.objs[-1] def add_path(self, layer, coordinates, width=None): """Connects a routing path on given layer,coordinates,width.""" debug.info(4, "add path " + str(layer) + " " + str(coordinates)) - import wire_path + from . import wire_path # NOTE: (UNTESTED) add_path(...) is currently not used - # lpp = techlayer[layer] + # lpp = tech_layer[layer] # self.objs.append(geometry.path(lpp, coordinates, width)) - wire_path.wire_path(obj=self, - layer=layer, - position_list=coordinates, - width=width) + wire_path(obj=self, + layer=layer, + position_list=coordinates, + width=width) def add_route(self, layers, coordinates, layer_widths): """Connects a routing path on given layer,coordinates,width. The @@ -961,13 +1196,13 @@ class layout(): preferred direction routing whereas this includes layers in the coordinates. """ - import route + from . import route debug.info(4, "add route " + str(layers) + " " + str(coordinates)) # add an instance of our path that breaks down into rectangles and contacts - route.route(obj=self, - layer_stack=layers, - path=coordinates, - layer_widths=layer_widths) + route(obj=self, + layer_stack=layers, + path=coordinates, + layer_widths=layer_widths) def add_zjog(self, layer, start, end, first_direction="H", var_offset=0.5, fixed_offset=None): """ @@ -994,9 +1229,9 @@ class layout(): else: debug.error("Invalid direction for jog -- must be H or V.") - if layer in layer_stacks: + if layer in tech_layer_stacks: self.add_wire(layer, [start, mid1, mid2, end]) - elif layer in techlayer: + elif layer in tech_layer: self.add_path(layer, [start, mid1, mid2, end]) else: debug.error("Could not find layer {}".format(layer)) @@ -1012,13 +1247,13 @@ class layout(): def add_wire(self, layers, coordinates, widen_short_wires=True): """Connects a routing path on given layer,coordinates,width. The layers are the (horizontal, via, vertical). """ - import wire + from . import wire # add an instance of our path that breaks down # into rectangles and contacts - wire.wire(obj=self, - layer_stack=layers, - position_list=coordinates, - widen_short_wires=widen_short_wires) + wire(obj=self, + layer_stack=layers, + position_list=coordinates, + widen_short_wires=widen_short_wires) def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None): """ Add a three layer via structure. """ @@ -1086,8 +1321,8 @@ class layout(): via = None cur_layer = from_layer while cur_layer != to_layer: - from_id = layer_indices[cur_layer] - to_id = layer_indices[to_layer] + from_id = tech_layer_indices[cur_layer] + to_id = tech_layer_indices[to_layer] if from_id < to_id: # grow the stack up search_id = 0 @@ -1096,7 +1331,7 @@ class layout(): search_id = 2 next_id = 0 - curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, layer_stacks), None) + curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, tech_layer_stacks), None) via = self.add_via_center(layers=curr_stack, size=size, @@ -1209,9 +1444,9 @@ class layout(): if not self.is_library_cell and not self.bounding_box: # If there is a boundary layer, and we didn't create one, add one. boundary_layers = [] - if "boundary" in techlayer.keys(): + if "boundary" in tech_layer.keys(): boundary_layers.append("boundary") - if "stdc" in techlayer.keys(): + if "stdc" in tech_layer.keys(): boundary_layers.append("stdc") boundary = [self.find_lowest_coords(), self.find_highest_coords()] @@ -1221,7 +1456,7 @@ class layout(): width = boundary[1][0] - boundary[0][0] for boundary_layer in boundary_layers: - (layer_number, layer_purpose) = techlayer[boundary_layer] + (layer_number, layer_purpose) = tech_layer[boundary_layer] gds_layout.addBox(layerNumber=layer_number, purposeNumber=layer_purpose, offsetInMicrons=boundary[0], @@ -1270,7 +1505,7 @@ class layout(): Do not write the pins since they aren't obstructions. """ if type(layer) == str: - lpp = techlayer[layer] + lpp = tech_layer[layer] else: lpp = layer @@ -1514,8 +1749,8 @@ class layout(): """ Wrapper to create a vertical channel route """ - import channel_route - cr = channel_route.channel_route(netlist, offset, layer_stack, directions, vertical=True, parent=self) + from .channel_route import channel_route + cr = channel_route(netlist, offset, layer_stack, directions, vertical=True, parent=self) # This causes problem in magic since it sometimes cannot extract connectivity of isntances # with no active devices. # self.add_inst(cr.name, cr) @@ -1526,8 +1761,8 @@ class layout(): """ Wrapper to create a horizontal channel route """ - import channel_route - cr = channel_route.channel_route(netlist, offset, layer_stack, directions, vertical=False, parent=self) + from .channel_route import channel_route + cr = channel_route(netlist, offset, layer_stack, directions, vertical=False, parent=self) # This causes problem in magic since it sometimes cannot extract connectivity of isntances # with no active devices. # self.add_inst(cr.name, cr) @@ -1540,9 +1775,9 @@ class layout(): return boundary_layers = [] - if "stdc" in techlayer.keys(): + if "stdc" in tech_layer.keys(): boundary_layers.append("stdc") - if "boundary" in techlayer.keys(): + if "boundary" in tech_layer.keys(): boundary_layers.append("boundary") # Save the last one as self.bounding_box for boundary_layer in boundary_layers: @@ -1791,7 +2026,7 @@ class layout(): def add_dnwell(self, bbox=None, inflate=1): """ Create a dnwell, along with nwell moat at border. """ - if "dnwell" not in techlayer: + if "dnwell" not in tech_layer: return if not bbox: diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index ee50ad4b..1216edc5 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -12,10 +12,10 @@ import math import tech from globals import OPTS from pprint import pformat -from delay_data import delay_data -from wire_spice_model import wire_spice_model -from power_data import power_data -import logical_effort +from .delay_data import delay_data +from .wire_spice_model import wire_spice_model +from .power_data import power_data +from .logical_effort import convert_relative_c_to_farad, convert_farad_to_relative_c class spice(): @@ -443,7 +443,7 @@ class spice(): # FIXME: Slew is not used in the model right now. # Can be added heuristically as linear factor - relative_cap = logical_effort.convert_farad_to_relative_c(load) + relative_cap = convert_farad_to_relative_c(load) stage_effort = self.get_stage_effort(relative_cap) # If it fails, then keep running with a valid object. @@ -511,7 +511,7 @@ class spice(): # Override this function within a module if a more accurate input capacitance is needed. # Input/outputs with differing capacitances is not implemented. relative_cap = self.input_load() - return logical_effort.convert_relative_c_to_farad(relative_cap) + return convert_relative_c_to_farad(relative_cap) def input_load(self): """Inform users undefined relative capacitance functions used for analytical delays.""" diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 8a54253f..799890e0 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug +from base import vector +from base import pin_layout from tech import layer_names import os import shutil from globals import OPTS -from vector import vector -from pin_layout import pin_layout class lef: diff --git a/compiler/characterizer/logical_effort.py b/compiler/base/logical_effort.py similarity index 97% rename from compiler/characterizer/logical_effort.py rename to compiler/base/logical_effort.py index 20225ebe..15f2b209 100644 --- a/compiler/characterizer/logical_effort.py +++ b/compiler/base/logical_effort.py @@ -6,7 +6,7 @@ # All rights reserved. # import debug -from tech import drc, parameter, spice +from tech import parameter class logical_effort(): """ @@ -81,4 +81,4 @@ def convert_farad_to_relative_c(c_farad): def convert_relative_c_to_farad(c_relative): """Converts capacitance in logical effort relative units to Femto-Farads.""" - return c_relative/parameter['cap_relative_per_ff'] \ No newline at end of file + return c_relative/parameter['cap_relative_per_ff'] diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index 82590ee6..f9b66612 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -7,7 +7,7 @@ # import debug from tech import GDS, drc -from vector import vector +from .vector import vector from tech import layer, layer_indices import math diff --git a/compiler/base/route.py b/compiler/base/route.py index 812318da..2a6376e3 100644 --- a/compiler/base/route.py +++ b/compiler/base/route.py @@ -5,12 +5,12 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from tech import drc import debug -from design import design +from .design import design +from .vector import vector +from .vector3d import vector3d +from tech import drc from itertools import tee -from vector import vector -from vector3d import vector3d from sram_factory import factory class route(design): diff --git a/compiler/base/utils.py b/compiler/base/utils.py index fe27c9c0..f80b23e3 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -8,12 +8,12 @@ import os import math -import gdsMill +from gdsMill import gdsMill import tech import globals import debug -from vector import vector -from pin_layout import pin_layout +from .vector import vector +from .pin_layout import pin_layout try: from tech import special_purposes except ImportError: diff --git a/compiler/router/vector3d.py b/compiler/base/vector3d.py similarity index 100% rename from compiler/router/vector3d.py rename to compiler/base/vector3d.py diff --git a/compiler/base/wire.py b/compiler/base/wire.py index 5c78755a..7114687c 100644 --- a/compiler/base/wire.py +++ b/compiler/base/wire.py @@ -6,8 +6,7 @@ # All rights reserved. # from tech import drc -import contact -from wire_path import wire_path +from .wire_path import wire_path from sram_factory import factory @@ -69,15 +68,24 @@ class wire(wire_path): This is contact direction independent pitch, i.e. we take the maximum contact dimension """ + + # This is here for the unit tests which may not have + # initialized the static parts of the layout class yet. + from base import layout + layout("fake", "fake") + (layer1, via, layer2) = layer_stack if layer1 == "poly" or layer1 == "active": - contact1 = getattr(contact, layer1 + "_contact") + try: + contact1 = getattr(layout, layer1 + "_contact") + except AttributeError: + breakpoint() else: try: - contact1 = getattr(contact, layer1 + "_via") + contact1 = getattr(layout, layer1 + "_via") except AttributeError: - contact1 = getattr(contact, layer2 + "_via") + contact1 = getattr(layout, layer2 + "_via") max_contact = max(contact1.width, contact1.height) layer1_space = drc("{0}_to_{0}".format(layer1)) diff --git a/compiler/base/wire_path.py b/compiler/base/wire_path.py index 411b9ede..363a41f3 100644 --- a/compiler/base/wire_path.py +++ b/compiler/base/wire_path.py @@ -5,11 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from .vector import vector +from .utils import snap_to_grid +from .design import design from tech import drc from tech import layer as techlayer -import debug -from vector import vector -from utils import snap_to_grid def create_rectilinear_route(my_list): """ Add intermediate nodes if it isn't rectilinear. Also skip diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index b0ee56f3..b2ccd79e 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -10,7 +10,7 @@ import math import tech from globals import OPTS from sram_factory import factory -import timing_graph +from base import timing_graph class simulation(): @@ -572,7 +572,7 @@ class simulation(): self.sram.graph_exclude_column_mux(self.bitline_column, port) # Generate new graph every analysis as edges might change depending on test bit - self.graph = timing_graph.timing_graph() + self.graph = timing_graph() self.sram_instance_name = "X{}".format(self.sram.name) self.sram.build_graph(self.graph, self.sram_instance_name, self.pins) diff --git a/compiler/datasheet/__init__.py b/compiler/datasheet/__init__.py new file mode 100644 index 00000000..369ba8fe --- /dev/null +++ b/compiler/datasheet/__init__.py @@ -0,0 +1 @@ +from .datasheet_gen import datasheet_gen diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 612a91df..d1fb3731 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -5,7 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from table_gen import * +from .table_gen import * import os import base64 from globals import OPTS diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 5a9e628b..f77458b4 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -19,8 +19,8 @@ from globals import OPTS import os import math import csv -import datasheet -import table_gen +from .datasheet import datasheet +from .table_gen import table_gen # def process_name(corner): # """ @@ -400,7 +400,7 @@ def parse_characterizer_csv(f, pages): if found == 0: # if this is the first corner for this sram, run first time configuration and set up tables - new_sheet = datasheet.datasheet(NAME) + new_sheet = datasheet(NAME) pages.append(new_sheet) new_sheet.git_id = ORIGIN_ID @@ -411,12 +411,12 @@ def parse_characterizer_csv(f, pages): new_sheet.description = [NAME, NUM_WORDS, NUM_BANKS, NUM_RW_PORTS, NUM_W_PORTS, NUM_R_PORTS, TECH_NAME, MIN_PERIOD, WORD_SIZE, ORIGIN_ID, DATETIME] - new_sheet.corners_table = table_gen.table_gen("corners") + new_sheet.corners_table = table_gen("corners") new_sheet.corners_table.add_row( ['Transistor Type', 'Power Supply', 'Temperature', 'Corner Name']) new_sheet.corners_table.add_row( [PROC, VOLT, TEMP, LIB_NAME.replace(OUT_DIR, '').replace(NAME, '')]) - new_sheet.operating_table = table_gen.table_gen( + new_sheet.operating_table = table_gen( "operating_table") new_sheet.operating_table.add_row( ['Parameter', 'Min', 'Typ', 'Max', 'Units']) @@ -432,10 +432,10 @@ def parse_characterizer_csv(f, pages): # failed to provide non-zero MIN_PERIOD new_sheet.operating_table.add_row( ['Operating Frequency (F)', '', '', "not available in netlist only", 'MHz']) - new_sheet.power_table = table_gen.table_gen("power") + new_sheet.power_table = table_gen("power") new_sheet.power_table.add_row( ['Pins', 'Mode', 'Power', 'Units']) - new_sheet.timing_table = table_gen.table_gen("timing") + new_sheet.timing_table = table_gen("timing") new_sheet.timing_table.add_row( ['Parameter', 'Min', 'Max', 'Units']) # parse initial timing information @@ -592,10 +592,10 @@ def parse_characterizer_csv(f, pages): else: break - new_sheet.dlv_table = table_gen.table_gen("dlv") + new_sheet.dlv_table = table_gen("dlv") new_sheet.dlv_table.add_row(['Type', 'Description', 'Link']) - new_sheet.io_table = table_gen.table_gen("io") + new_sheet.io_table = table_gen("io") new_sheet.io_table.add_row(['Type', 'Value']) if not OPTS.netlist_only: diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py index cc0d215e..99e70411 100644 --- a/compiler/datasheet/table_gen.py +++ b/compiler/datasheet/table_gen.py @@ -5,6 +5,8 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # + + class table_gen: """small library of functions to generate the html tables""" diff --git a/compiler/drc/__init__.py b/compiler/drc/__init__.py new file mode 100644 index 00000000..40e3a45c --- /dev/null +++ b/compiler/drc/__init__.py @@ -0,0 +1,6 @@ +from .custom_cell_properties import * +from .custom_layer_properties import * +from .design_rules import * +from .module_type import * +from .drc_lut import * +from .drc_value import * diff --git a/compiler/base/custom_cell_properties.py b/compiler/drc/custom_cell_properties.py similarity index 100% rename from compiler/base/custom_cell_properties.py rename to compiler/drc/custom_cell_properties.py diff --git a/compiler/base/custom_layer_properties.py b/compiler/drc/custom_layer_properties.py similarity index 100% rename from compiler/base/custom_layer_properties.py rename to compiler/drc/custom_layer_properties.py diff --git a/compiler/drc/design_rules.py b/compiler/drc/design_rules.py index 56d0e8b6..dfa23c2a 100644 --- a/compiler/drc/design_rules.py +++ b/compiler/drc/design_rules.py @@ -6,8 +6,8 @@ # All rights reserved. # import debug -from drc_value import * -from drc_lut import * +from .drc_value import * +from .drc_lut import * class design_rules(dict): diff --git a/compiler/modules/module_type.py b/compiler/drc/module_type.py similarity index 100% rename from compiler/modules/module_type.py rename to compiler/drc/module_type.py diff --git a/compiler/globals.py b/compiler/globals.py index d0c0d673..c216858e 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -252,7 +252,8 @@ def setup_bitcell(): # See if bitcell exists try: - __import__(OPTS.bitcell) + c = importlib.import_module("modules." + OPTS.bitcell) + mod = getattr(c, OPTS.bitcell) except ImportError: # Use the pbitcell if we couldn't find a custom bitcell # or its custom replica bitcell @@ -430,19 +431,12 @@ def setup_paths(): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) except: debug.error("$OPENRAM_HOME is not properly defined.", 1) + debug.check(os.path.isdir(OPENRAM_HOME), "$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME)) - # Add all of the subdirs to the python path - # These subdirs are modules and don't need - # to be added: characterizer, verify - subdirlist = [item for item in os.listdir(OPENRAM_HOME) if os.path.isdir(os.path.join(OPENRAM_HOME, item))] - for subdir in subdirlist: - full_path = "{0}/{1}".format(OPENRAM_HOME, subdir) - debug.check(os.path.isdir(full_path), - "$OPENRAM_HOME/{0} does not exist: {1}".format(subdir, full_path)) - if "__pycache__" not in full_path: - sys.path.append("{0}".format(full_path)) + if OPENRAM_HOME not in sys.path: + debug.error("Please add OPENRAM_HOME to the PYTHONPATH.", -1) # Use a unique temp subdirectory if multithreaded if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp": @@ -569,18 +563,18 @@ def import_tech(): OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/" - # Add the tech directory + # Prepend the tech directory so it is sourced FIRST tech_path = OPTS.openram_tech - sys.path.append(tech_path) + sys.path.insert(0, tech_path) try: import tech except ImportError: debug.error("Could not load tech module.", -1) - # Add custom modules of the technology to the path, if they exist + # Prepend custom modules of the technology to the path, if they exist custom_mod_path = os.path.join(tech_path, "modules/") if os.path.exists(custom_mod_path): - sys.path.append(custom_mod_path) + sys.path.insert(0, custom_mod_path) def print_time(name, now_time, last_time=None, indentation=2): diff --git a/compiler/modules/__init__.py b/compiler/modules/__init__.py new file mode 100644 index 00000000..b2f78ba7 --- /dev/null +++ b/compiler/modules/__init__.py @@ -0,0 +1,82 @@ +from .and2_dec import * +from .and3_dec import * +from .and4_dec import * +from .bank import * +from .bitcell_1port import * +from .bitcell_2port import * +from .bitcell_array import * +from .bitcell_base_array import * +from .bitcell_base import * +from .col_cap_array import * +from .col_cap_bitcell_1port import * +from .col_cap_bitcell_2port import * +from .column_decoder import * +from .column_mux_array import * +from .column_mux import * +from .control_logic import * +from .delay_chain import * +from .dff_array import * +from .dff_buf_array import * +from .dff_buf import * +from .dff_inv_array import * +from .dff_inv import * +from .dff import * +from .dummy_array import * +from .dummy_bitcell_1port import * +from .dummy_bitcell_2port import * +from .dummy_pbitcell import * +from .global_bitcell_array import * +from .hierarchical_decoder import * +from .hierarchical_predecode2x4 import * +from .hierarchical_predecode3x8 import * +from .hierarchical_predecode4x16 import * +from .hierarchical_predecode import * +from .inv_dec import * +from .local_bitcell_array import * +from .nand2_dec import * +from .nand3_dec import * +from .nand4_dec import * +from .orig_bitcell_array import * +from .pand2 import * +from .pand3 import * +from .pand4 import * +from .pbitcell import * +from .pbuf_dec import * +from .pbuf import * +from .pdriver import * +from .pgate import * +from .pinvbuf import * +from .pinv_dec import * +from .pinv import * +from .pnand2 import * +from .pnand3 import * +from .pnand4 import * +from .pnor2 import * +from .port_address import * +from .port_data import * +from .precharge_array import * +from .precharge import * +from .ptristate_inv import * +from .ptx import * +from .pwrite_driver import * +from .replica_bitcell_1port import * +from .replica_bitcell_2port import * +from .replica_bitcell_array import * +from .replica_column import * +from .replica_pbitcell import * +from .row_cap_array import * +from .row_cap_bitcell_1port import * +from .row_cap_bitcell_2port import * +from .sense_amp_array import * +from .sense_amp import * +from .tri_gate_array import * +from .tri_gate import * +from .wordline_buffer_array import * +from .wordline_driver_array import * +from .wordline_driver import * +from .write_driver_array import * +from .write_driver import * +from .write_mask_and_array import * +from .sram_1bank import * +from .sram_config import * +from .sram import * diff --git a/compiler/modules/and2_dec.py b/compiler/modules/and2_dec.py index 92130b7b..8ce10caa 100644 --- a/compiler/modules/and2_dec.py +++ b/compiler/modules/and2_dec.py @@ -6,20 +6,20 @@ # All rights reserved. # import debug -from vector import vector -import design +from base import vector +from base import design from sram_factory import factory from globals import OPTS from tech import layer -class and2_dec(design.design): +class and2_dec(design): """ This is an AND with configurable drive strength. """ def __init__(self, name, size=1, height=None, add_wells=True): - design.design.__init__(self, name) + design.__init__(self, name) debug.info(1, "Creating and2_dec {}".format(name)) self.add_comment("size: {}".format(size)) diff --git a/compiler/modules/and3_dec.py b/compiler/modules/and3_dec.py index 6f788824..9c8ee348 100644 --- a/compiler/modules/and3_dec.py +++ b/compiler/modules/and3_dec.py @@ -6,19 +6,19 @@ # All rights reserved. # import debug -from vector import vector -import design +from base import design +from base import vector from sram_factory import factory from globals import OPTS from tech import layer -class and3_dec(design.design): +class and3_dec(design): """ This is an AND with configurable drive strength. """ def __init__(self, name, size=1, height=None, add_wells=True): - design.design.__init__(self, name) + design.__init__(self, name) debug.info(1, "Creating and3_dec {}".format(name)) self.add_comment("size: {}".format(size)) self.size = size diff --git a/compiler/modules/and4_dec.py b/compiler/modules/and4_dec.py index 879f581b..6d75eedd 100644 --- a/compiler/modules/and4_dec.py +++ b/compiler/modules/and4_dec.py @@ -6,20 +6,20 @@ # All rights reserved. # import debug -from vector import vector -import design +from base import design +from base import vector from sram_factory import factory from globals import OPTS from tech import layer -class and4_dec(design.design): +class and4_dec(design): """ This is an AND with configurable drive strength. """ def __init__(self, name, size=1, height=None, add_wells=True): - design.design.__init__(self, name) + design.__init__(self, name) debug.info(1, "Creating and4_dec {}".format(name)) self.add_comment("size: {}".format(size)) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 1f807d63..88d8abc7 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -6,16 +6,16 @@ # All rights reserved. # import debug -import design +from base import design +from base import vector from sram_factory import factory from math import log, ceil, floor from tech import drc -from vector import vector from globals import OPTS from tech import layer_properties as layer_props -class bank(design.design): +class bank(design): """ Dynamically generated a single bank including bitcell array, hierarchical_decoder, precharge, (optional column_mux and column decoder), diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 9b375c00..4d299c6e 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -5,19 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import sys -from tech import drc, parameter -import debug -import design -import contact -from pinv import pinv -from pnand2 import pnand2 -from pnor2 import pnor2 -from vector import vector +from tech import drc +from base import design +from base import vector +from pgates import pinv +from pgates import pnand2 +from pgates import pnor2 from sram_factory import factory from globals import OPTS -class bank_select(design.design): +class bank_select(design): """Create a bank select signal that is combined with an array of NOR+INV gates to gate the control signals in case of multiple banks are created in upper level SRAM module diff --git a/compiler/bitcells/bitcell_1port.py b/compiler/modules/bitcell_1port.py similarity index 93% rename from compiler/bitcells/bitcell_1port.py rename to compiler/modules/bitcell_1port.py index 12c3c3ce..ed8bc8f3 100644 --- a/compiler/bitcells/bitcell_1port.py +++ b/compiler/modules/bitcell_1port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class bitcell_1port(bitcell_base.bitcell_base): +class bitcell_1port(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so diff --git a/compiler/bitcells/bitcell_2port.py b/compiler/modules/bitcell_2port.py similarity index 97% rename from compiler/bitcells/bitcell_2port.py rename to compiler/modules/bitcell_2port.py index 75d654c0..86eddf7e 100644 --- a/compiler/bitcells/bitcell_2port.py +++ b/compiler/modules/bitcell_2port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class bitcell_2port(bitcell_base.bitcell_base): +class bitcell_2port(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so @@ -103,4 +103,4 @@ class bitcell_2port(bitcell_base.bitcell_base): def is_non_inverting(self): """Return input to output polarity for module""" - return False \ No newline at end of file + return False diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 0432dec2..e50c5b73 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -6,7 +6,7 @@ # All rights reserved. # import debug -from bitcell_base_array import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from tech import drc, spice from globals import OPTS from sram_factory import factory diff --git a/compiler/bitcells/bitcell_base.py b/compiler/modules/bitcell_base.py similarity index 95% rename from compiler/bitcells/bitcell_base.py rename to compiler/modules/bitcell_base.py index 30e09825..ec2e108e 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/modules/bitcell_base.py @@ -7,18 +7,18 @@ # import debug -import design +from base import design from globals import OPTS -import logical_effort +from base import logical_effort from tech import parameter, drc, layer, spice -class bitcell_base(design.design): +class bitcell_base(design): """ Base bitcell parameters to be over-riden. """ def __init__(self, name, cell_name=None, prop=None): - design.design.__init__(self, name, cell_name, prop) + design.__init__(self, name, cell_name, prop) # Set the bitcell specific properties if prop: @@ -37,12 +37,12 @@ class bitcell_base(design.design): # min size NMOS gate load read_port_load = 0.5 - return logical_effort.logical_effort('bitline', - size, - cin, - load + read_port_load, - parasitic_delay, - False) + return logical_effort('bitline', + size, + cin, + load + read_port_load, + parasitic_delay, + False) def analytical_power(self, corner, load): """Bitcell power in nW. Only characterizes leakage.""" @@ -264,4 +264,4 @@ class bitcell_base(design.design): else: delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m) - return delay \ No newline at end of file + return delay diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 45285267..062a74a0 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -import design +from base import design from sram_factory import factory from globals import OPTS -class bitcell_base_array(design.design): +class bitcell_base_array(design): """ Abstract base class for bitcell-arrays -- bitcell, dummy, replica """ diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 27194a89..158cf04b 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -3,7 +3,7 @@ # Copyright (c) 2016-2021 Regents of the University of California # All rights reserved. # -from bitcell_base_array import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from sram_factory import factory from globals import OPTS diff --git a/compiler/bitcells/col_cap_bitcell_1port.py b/compiler/modules/col_cap_bitcell_1port.py similarity index 88% rename from compiler/bitcells/col_cap_bitcell_1port.py rename to compiler/modules/col_cap_bitcell_1port.py index d2771e6d..b57cfa3f 100644 --- a/compiler/bitcells/col_cap_bitcell_1port.py +++ b/compiler/modules/col_cap_bitcell_1port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class col_cap_bitcell_1port(bitcell_base.bitcell_base): +class col_cap_bitcell_1port(bitcell_base): """ Column end cap cell. """ diff --git a/compiler/bitcells/col_cap_bitcell_2port.py b/compiler/modules/col_cap_bitcell_2port.py similarity index 88% rename from compiler/bitcells/col_cap_bitcell_2port.py rename to compiler/modules/col_cap_bitcell_2port.py index 71b27619..acc0e489 100644 --- a/compiler/bitcells/col_cap_bitcell_2port.py +++ b/compiler/modules/col_cap_bitcell_2port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class col_cap_bitcell_2port(bitcell_base.bitcell_base): +class col_cap_bitcell_2port(bitcell_base): """ Column end cap cell. """ diff --git a/compiler/modules/column_decoder.py b/compiler/modules/column_decoder.py index f94786a2..2c7199b8 100644 --- a/compiler/modules/column_decoder.py +++ b/compiler/modules/column_decoder.py @@ -5,16 +5,16 @@ # from tech import drc import debug -import design +from base import design import math from sram_factory import factory -from vector import vector +from base import vector from globals import OPTS from tech import cell_properties from tech import layer_properties as layer_props -class column_decoder(design.design): +class column_decoder(design): """ Create the column mux decoder. """ diff --git a/compiler/pgates/column_mux.py b/compiler/modules/column_mux.py similarity index 99% rename from compiler/pgates/column_mux.py rename to compiler/modules/column_mux.py index bf489e87..67c44894 100644 --- a/compiler/pgates/column_mux.py +++ b/compiler/modules/column_mux.py @@ -5,16 +5,17 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import pgate +from .pgate import * import debug from tech import drc, layer -from vector import vector +from base import vector +from .pgate import * from sram_factory import factory from tech import cell_properties as cell_props from globals import OPTS -class column_mux(pgate.pgate): +class column_mux(pgate): """ This module implements the columnmux bitline cell used in the design. Creates a single column mux cell with the given integer size relative diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py index 36d4080e..fa264d37 100644 --- a/compiler/modules/column_mux_array.py +++ b/compiler/modules/column_mux_array.py @@ -5,16 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug from tech import layer, preferred_directions -from vector import vector +from base import vector from sram_factory import factory from globals import OPTS from tech import layer_properties as layer_props -class column_mux_array(design.design): +class column_mux_array(design): """ Dynamically generated column mux array. Array of column mux to read the bitlines through the 6T. diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 79ce3e30..e7c1d345 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -5,16 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug from sram_factory import factory import math -from vector import vector +from base import vector from globals import OPTS -import logical_effort +from base import logical_effort -class control_logic(design.design): +class control_logic(design): """ Dynamically generated Control logic for the total SRAM circuit. """ @@ -43,7 +43,7 @@ class control_logic(design.design): self.num_words = num_rows * words_per_row self.enable_delay_chain_resizing = False - self.inv_parasitic_delay = logical_effort.logical_effort.pinv + self.inv_parasitic_delay = logical_effort.pinv # Determines how much larger the sen delay should be. Accounts for possible error in model. # FIXME: This should be made a parameter diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index f90191ef..c393e280 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class delay_chain(design.design): +class delay_chain(design): """ Generate a delay chain with the given number of stages and fanout. Input is a list contains the electrical effort (fanout) of each stage. diff --git a/compiler/custom/dff.py b/compiler/modules/dff.py similarity index 96% rename from compiler/custom/dff.py rename to compiler/modules/dff.py index 33bd2b3a..0f7cb777 100644 --- a/compiler/custom/dff.py +++ b/compiler/modules/dff.py @@ -5,12 +5,12 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design from tech import cell_properties as props from tech import spice -class dff(design.design): +class dff(design): """ Memory address flip-flop """ diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 86805407..5a9070c7 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from sram_factory import factory from globals import OPTS -class dff_array(design.design): +class dff_array(design): """ This is a simple row (or multiple rows) of flops. Unlike the data flops, these are never spaced out. diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 9ff31bae..b0cd619c 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -6,14 +6,14 @@ # All rights reserved. # import debug -import design +from base import design from tech import layer -from vector import vector +from base import vector from globals import OPTS from sram_factory import factory -class dff_buf(design.design): +class dff_buf(design): """ This is a simple buffered DFF. The output is buffered with two inverters, of variable size, to provide q diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 6c8f88de..e284b589 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class dff_buf_array(design.design): +class dff_buf_array(design): """ This is a simple row (or multiple rows) of flops. Unlike the data flops, these are never spaced out. diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 840ba40f..4d162c23 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class dff_inv(design.design): +class dff_inv(design): """ This is a simple DFF with an inverted output. Some DFFs do not have Qbar, so this will create it. diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 20d59939..97cbd590 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class dff_inv_array(design.design): +class dff_inv_array(design): """ This is a simple row (or multiple rows) of flops. Unlike the data flops, these are never spaced out. diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 83449a70..566122e7 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -3,7 +3,7 @@ # Copyright (c) 2016-2021 Regents of the University of California # All rights reserved. # -from bitcell_base_array import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from sram_factory import factory from globals import OPTS diff --git a/compiler/bitcells/dummy_bitcell_1port.py b/compiler/modules/dummy_bitcell_1port.py similarity index 89% rename from compiler/bitcells/dummy_bitcell_1port.py rename to compiler/modules/dummy_bitcell_1port.py index 6573394e..3c6f9da6 100644 --- a/compiler/bitcells/dummy_bitcell_1port.py +++ b/compiler/modules/dummy_bitcell_1port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class dummy_bitcell_1port(bitcell_base.bitcell_base): +class dummy_bitcell_1port(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so diff --git a/compiler/bitcells/dummy_bitcell_2port.py b/compiler/modules/dummy_bitcell_2port.py similarity index 89% rename from compiler/bitcells/dummy_bitcell_2port.py rename to compiler/modules/dummy_bitcell_2port.py index a1a96810..94f99f39 100644 --- a/compiler/bitcells/dummy_bitcell_2port.py +++ b/compiler/modules/dummy_bitcell_2port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class dummy_bitcell_2port(bitcell_base.bitcell_base): +class dummy_bitcell_2port(bitcell_base): """ A single bit cell which is forced to store a 0. This module implements the single memory cell used in the design. It diff --git a/compiler/bitcells/dummy_pbitcell.py b/compiler/modules/dummy_pbitcell.py similarity index 96% rename from compiler/bitcells/dummy_pbitcell.py rename to compiler/modules/dummy_pbitcell.py index 7cf8f664..7b099218 100644 --- a/compiler/bitcells/dummy_pbitcell.py +++ b/compiler/modules/dummy_pbitcell.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class dummy_pbitcell(design.design): +class dummy_pbitcell(design): """ Creates a replica bitcell using pbitcell """ @@ -23,7 +23,7 @@ class dummy_pbitcell(design.design): self.num_r_ports = OPTS.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - design.design.__init__(self, name) + design.__init__(self, name) debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports)) diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 9c493e55..b25c37de 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -5,16 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from globals import OPTS from sram_factory import factory -from vector import vector +from base import vector import debug from numpy import cumsum from tech import layer_properties as layer_props -class global_bitcell_array(bitcell_base_array.bitcell_base_array): +class global_bitcell_array(bitcell_base_array): """ Creates a global bitcell array. Rows is an integer number for all local arrays. diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 40c2a93a..52b71229 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -6,17 +6,17 @@ # All rights reserved. # import debug -import design +from base import design import math from sram_factory import factory -from vector import vector +from base import vector from globals import OPTS from tech import layer_indices from tech import layer_stacks from tech import layer_properties as layer_props from tech import drc -class hierarchical_decoder(design.design): +class hierarchical_decoder(design): """ Dynamically generated hierarchical decoder. """ diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 1431d75c..867b113b 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -6,9 +6,9 @@ # All rights reserved. # import debug -import design +from base import design import math -from vector import vector +from base import vector from sram_factory import factory from globals import OPTS from tech import layer_properties as layer_props @@ -18,7 +18,7 @@ from tech import preferred_directions from tech import drc -class hierarchical_predecode(design.design): +class hierarchical_predecode(design): """ Pre 2x4 and 3x8 and TBD 4x16 decoder shared code. """ diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 941a0756..bdd01499 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -5,7 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from hierarchical_predecode import hierarchical_predecode +from .hierarchical_predecode import hierarchical_predecode from globals import OPTS diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index ef70a282..dc8e026c 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -5,7 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from hierarchical_predecode import hierarchical_predecode +from .hierarchical_predecode import hierarchical_predecode from globals import OPTS diff --git a/compiler/modules/hierarchical_predecode4x16.py b/compiler/modules/hierarchical_predecode4x16.py index 64eef96d..7227bf3b 100644 --- a/compiler/modules/hierarchical_predecode4x16.py +++ b/compiler/modules/hierarchical_predecode4x16.py @@ -5,7 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from hierarchical_predecode import hierarchical_predecode +from .hierarchical_predecode import hierarchical_predecode from globals import OPTS diff --git a/compiler/custom/inv_dec.py b/compiler/modules/inv_dec.py similarity index 82% rename from compiler/custom/inv_dec.py rename to compiler/modules/inv_dec.py index d963783f..8f143e29 100644 --- a/compiler/custom/inv_dec.py +++ b/compiler/modules/inv_dec.py @@ -5,13 +5,13 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design -import logical_effort +from base import design +from base import logical_effort from tech import cell_properties as props from tech import spice, parameter -class inv_dec(design.design): +class inv_dec(design): """ INV for address decoders. """ @@ -51,12 +51,12 @@ class inv_dec(design.design): Input inverted by this stage. """ parasitic_delay = 1 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 18b33c0f..ba253e9d 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -5,15 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from globals import OPTS from sram_factory import factory -from vector import vector +from base import vector import debug from tech import layer_properties as layer_props -class local_bitcell_array(bitcell_base_array.bitcell_base_array): +class local_bitcell_array(bitcell_base_array): """ A local bitcell array is a bitcell array with a wordline driver. This can either be a single aray on its own if there is no hierarchical WL diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 45f46496..e5c4bbfc 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -8,15 +8,14 @@ import sys from tech import drc, parameter import debug -import design +from base import design import math from math import log,sqrt,ceil -import contact -from vector import vector +from base import vector from sram_factory import factory from globals import OPTS -class multibank(design.design): +class multibank(design): """ Dynamically generated a single bank including bitcell array, hierarchical_decoder, precharge, (optional column_mux and column decoder), @@ -799,7 +798,7 @@ class multibank(design.design): self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) # Bring it up to M2 for M2/M3 routing self.add_via(layers=self.m1_stack, - offset=in_pin + contact.m1_via.offset, + offset=in_pin + self.m1_via.offset, rotate=90) self.add_via(layers=self.m2_stack, offset=in_pin + self.m2m3_via_offset, @@ -812,7 +811,7 @@ class multibank(design.design): rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y) self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) self.add_via(layers=self.m1_stack, - offset=in_pin + contact.m1_via.offset, + offset=in_pin + self.m1_via.offset, rotate=90) self.add_via(layers=self.m2_stack, offset=in_pin + self.m2m3_via_offset, diff --git a/compiler/custom/nand2_dec.py b/compiler/modules/nand2_dec.py similarity index 87% rename from compiler/custom/nand2_dec.py rename to compiler/modules/nand2_dec.py index 33b7729b..493facb8 100644 --- a/compiler/custom/nand2_dec.py +++ b/compiler/modules/nand2_dec.py @@ -5,13 +5,13 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design from tech import spice, parameter, drc from tech import cell_properties as props -import logical_effort +from base import logical_effort -class nand2_dec(design.design): +class nand2_dec(design): """ 2-input NAND decoder for address decoders. """ @@ -56,12 +56,12 @@ class nand2_dec(design.design): Input inverted by this stage. """ parasitic_delay = 2 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ @@ -96,4 +96,4 @@ class nand2_dec(design.design): pmos_drain_c = self.drain_c_(self.pmos_width*mult, 1, mult) - return nmos_drain_c + pmos_drain_c \ No newline at end of file + return nmos_drain_c + pmos_drain_c diff --git a/compiler/custom/nand3_dec.py b/compiler/modules/nand3_dec.py similarity index 87% rename from compiler/custom/nand3_dec.py rename to compiler/modules/nand3_dec.py index af0d2f1f..08978d46 100644 --- a/compiler/custom/nand3_dec.py +++ b/compiler/modules/nand3_dec.py @@ -5,13 +5,13 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design from tech import spice, parameter, drc from tech import cell_properties as props -import logical_effort +from base import logical_effort -class nand3_dec(design.design): +class nand3_dec(design): """ 3-input NAND decoder for address decoders. """ @@ -56,12 +56,12 @@ class nand3_dec(design.design): Input inverted by this stage. """ parasitic_delay = 2 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ @@ -96,4 +96,4 @@ class nand3_dec(design.design): pmos_drain_c = self.drain_c_(self.pmos_width*mult, 1, mult) - return nmos_drain_c + pmos_drain_c \ No newline at end of file + return nmos_drain_c + pmos_drain_c diff --git a/compiler/custom/nand4_dec.py b/compiler/modules/nand4_dec.py similarity index 87% rename from compiler/custom/nand4_dec.py rename to compiler/modules/nand4_dec.py index a4afadbe..8dd4a039 100644 --- a/compiler/custom/nand4_dec.py +++ b/compiler/modules/nand4_dec.py @@ -5,13 +5,13 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design from tech import spice, parameter, drc from tech import cell_properties as props -import logical_effort +from base import logical_effort -class nand4_dec(design.design): +class nand4_dec(design): """ 4-input NAND decoder for address decoders. """ @@ -56,12 +56,12 @@ class nand4_dec(design.design): Input inverted by this stage. """ parasitic_delay = 2 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ @@ -96,4 +96,4 @@ class nand4_dec(design.design): pmos_drain_c = self.drain_c_(self.pmos_width*mult, 1, mult) - return nmos_drain_c + pmos_drain_c \ No newline at end of file + return nmos_drain_c + pmos_drain_c diff --git a/compiler/modules/orig_bitcell_array.py b/compiler/modules/orig_bitcell_array.py index ab154bec..2e3088af 100644 --- a/compiler/modules/orig_bitcell_array.py +++ b/compiler/modules/orig_bitcell_array.py @@ -5,7 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from bitcell_base_array import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from tech import drc, spice from globals import OPTS from sram_factory import factory diff --git a/compiler/pgates/pand2.py b/compiler/modules/pand2.py similarity index 98% rename from compiler/pgates/pand2.py rename to compiler/modules/pand2.py index ab601096..8bd17589 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/modules/pand2.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -from vector import vector -import pgate +from base import vector +from .pgate import * from sram_factory import factory -class pand2(pgate.pgate): +class pand2(pgate): """ This is an AND (or NAND) with configurable drive strength. """ diff --git a/compiler/pgates/pand3.py b/compiler/modules/pand3.py similarity index 98% rename from compiler/pgates/pand3.py rename to compiler/modules/pand3.py index 477872c8..f63b8c41 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/modules/pand3.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -from vector import vector -import pgate +from base import vector +from .pgate import * from sram_factory import factory -class pand3(pgate.pgate): +class pand3(pgate): """ This is a simple buffer used for driving loads. """ diff --git a/compiler/pgates/pand4.py b/compiler/modules/pand4.py similarity index 98% rename from compiler/pgates/pand4.py rename to compiler/modules/pand4.py index 8911364c..9b5a31d6 100644 --- a/compiler/pgates/pand4.py +++ b/compiler/modules/pand4.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -from vector import vector -import pgate +from base import vector +from .pgate import * from sram_factory import factory -class pand4(pgate.pgate): +class pand4(pgate): """ This is a simple buffer used for driving loads. """ diff --git a/compiler/bitcells/pbitcell.py b/compiler/modules/pbitcell.py similarity index 96% rename from compiler/bitcells/pbitcell.py rename to compiler/modules/pbitcell.py index d1e7927b..516dca3f 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/modules/pbitcell.py @@ -5,18 +5,17 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact import debug +from base import logical_effort +from base import vector from tech import drc, parameter, layer from tech import cell_properties as props -from vector import vector -from ptx import ptx from globals import OPTS -import logical_effort -import bitcell_base +from .ptx import ptx +from .bitcell_base import bitcell_base -class pbitcell(bitcell_base.bitcell_base): +class pbitcell(bitcell_base): """ This module implements a parametrically sized multi-port bitcell, with a variable number of read/write, write, and read ports @@ -45,7 +44,7 @@ class pbitcell(bitcell_base.bitcell_base): self.gnd_layer = "m1" self.gnd_dir = "H" - bitcell_base.bitcell_base.__init__(self, name) + bitcell_base.__init__(self, name) fmt_str = "{0} rw ports, {1} w ports and {2} r ports" info_string = fmt_str.format(self.num_rw_ports, self.num_w_ports, @@ -222,20 +221,20 @@ class pbitcell(bitcell_base.bitcell_base): # y-offset for the access transistor's gate contact self.gate_contact_yoffset = max_contact_extension + self.m2_space \ - + 0.5 * max(contact.poly_contact.height, contact.m1_via.height) + + 0.5 * max(self.poly_contact.height, self.m1_via.height) # y-position of access transistors - self.port_ypos = self.m1_space + 0.5 * contact.m1_via.height + self.gate_contact_yoffset + self.port_ypos = self.m1_space + 0.5 * self.m1_via.height + self.gate_contact_yoffset # y-position of inverter nmos self.inverter_nmos_ypos = self.port_ypos # spacing between ports (same for read/write and write ports) self.bitline_offset = -0.5 * self.readwrite_nmos.active_width \ - + 0.5 * contact.m1_via.height \ + + 0.5 * self.m1_via.height \ + self.m2_space + self.m2_width m2_constraint = self.bitline_offset + self.m2_space \ - + 0.5 * contact.m1_via.height \ + + 0.5 * self.m1_via.height \ - 0.5 * self.readwrite_nmos.active_width self.write_port_spacing = max(self.active_space, self.m1_space, @@ -243,7 +242,7 @@ class pbitcell(bitcell_base.bitcell_base): self.read_port_spacing = self.bitline_offset + self.m2_space # spacing between cross coupled inverters - self.inverter_to_inverter_spacing = contact.poly_contact.width + self.m1_space + self.inverter_to_inverter_spacing = self.poly_contact.width + self.m1_space # calculations related to inverter connections inverter_pmos_contact_extension = 0.5 * \ @@ -252,19 +251,19 @@ class pbitcell(bitcell_base.bitcell_base): (self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_contact + 2 * contact.poly_contact.width \ + + self.poly_to_contact + 2 * self.poly_contact.width \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + 0.5 * contact.poly_contact.width + + 0.5 * self.poly_contact.width self.cross_couple_upper_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ + self.poly_to_contact \ - + 1.5 * contact.poly_contact.width + + 1.5 * self.poly_contact.width # spacing between wordlines (and gnd) self.m1_offset = -0.5 * self.m1_width @@ -300,7 +299,7 @@ class pbitcell(bitcell_base.bitcell_base): (self.write_nmos.active_width + self.write_port_spacing) \ - self.num_r_ports * \ (self.read_port_width + self.read_port_spacing) \ - - self.bitline_offset - 0.5 * contact.m1_via.width + - self.bitline_offset - 0.5 * self.m1_via.width self.width = -2 * self.leftmost_xpos self.height = self.topmost_ypos - self.botmost_ypos @@ -390,14 +389,14 @@ class pbitcell(bitcell_base.bitcell_base): # add contacts to connect gate poly to drain/source # metal1 (to connect Q to Q_bar) contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x \ - + 0.5 * contact.poly_contact.height, + + 0.5 * self.poly_contact.height, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_left, directions=("H", "H")) contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - - 0.5*contact.poly_contact.height, + - 0.5*self.poly_contact.height, self.cross_couple_lower_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_right, @@ -414,11 +413,11 @@ class pbitcell(bitcell_base.bitcell_base): if OPTS.use_pex: # add labels to cross couple inverter for extracted simulation contact_offset_left_output = vector(self.inverter_nmos_left.get_pin("D").rc().x \ - + 0.5 * contact.poly.height, + + 0.5 * self.poly.height, self.cross_couple_upper_ypos) contact_offset_right_output = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - - 0.5*contact.poly.height, + - 0.5*self.poly.height, self.cross_couple_lower_ypos) self.add_pex_labels(contact_offset_left_output, contact_offset_right_output) @@ -896,7 +895,7 @@ class pbitcell(bitcell_base.bitcell_base): directions="nonpref") self.add_path("m2", - [port_contact_offest, bl_offset], width=contact.m1_via.height) + [port_contact_offest, bl_offset], width=self.m1_via.height) for k in range(self.total_ports): port_contact_offest = right_port_transistors[k].get_pin("D").center() @@ -909,7 +908,7 @@ class pbitcell(bitcell_base.bitcell_base): directions="nonpref") self.add_path("m2", - [port_contact_offest, br_offset], width=contact.m1_via.height) + [port_contact_offest, br_offset], width=self.m1_via.height) def route_supplies(self): """ Route inverter nmos and read-access nmos to gnd. Route inverter pmos to vdd. """ @@ -928,9 +927,9 @@ class pbitcell(bitcell_base.bitcell_base): if position.x > 0: - contact_correct = 0.5 * contact.m1_via.height + contact_correct = 0.5 * self.m1_via.height else: - contact_correct = -0.5 * contact.m1_via.height + contact_correct = -0.5 * self.m1_via.height supply_offset = vector(position.x + contact_correct, self.gnd_position.y) self.add_via_center(layers=self.m1_stack, @@ -997,7 +996,7 @@ class pbitcell(bitcell_base.bitcell_base): """ # add poly to metal1 contacts for gates of the inverters left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - - self.poly_to_contact - 0.5*contact.poly_contact.width, + - self.poly_to_contact - 0.5*self.poly_contact.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=left_storage_contact, @@ -1005,7 +1004,7 @@ class pbitcell(bitcell_base.bitcell_base): right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ - + self.poly_to_contact + 0.5*contact.poly_contact.width, + + self.poly_to_contact + 0.5*self.poly_contact.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=right_storage_contact, @@ -1192,12 +1191,12 @@ class pbitcell(bitcell_base.bitcell_base): # min size NMOS gate load read_port_load = self.num_r_ports / 2 total_load = load + read_port_load + write_port_load - return logical_effort.logical_effort('bitline', - size, - cin, - load + read_port_load, - parasitic_delay, - False) + return logical_effort('bitline', + size, + cin, + load + read_port_load, + parasitic_delay, + False) def input_load(self): """ Return the relative capacitance of the access transistor gates """ diff --git a/compiler/pgates/pbuf.py b/compiler/modules/pbuf.py similarity index 98% rename from compiler/pgates/pbuf.py rename to compiler/modules/pbuf.py index 5ed11f39..ba44fe2f 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/modules/pbuf.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -from vector import vector -import pgate +from base import vector +from .pgate import * from sram_factory import factory -class pbuf(pgate.pgate): +class pbuf(pgate): """ This is a simple buffer used for driving loads. """ diff --git a/compiler/pgates/pbuf_dec.py b/compiler/modules/pbuf_dec.py similarity index 96% rename from compiler/pgates/pbuf_dec.py rename to compiler/modules/pbuf_dec.py index a0cbafca..c04d4922 100644 --- a/compiler/pgates/pbuf_dec.py +++ b/compiler/modules/pbuf_dec.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -from vector import vector -import pgate +from base import vector +from .pgate import * from sram_factory import factory -class pbuf_dec(pgate.pgate): +class pbuf_dec(pgate): """ This is a simple buffer used for driving wordlines. """ @@ -25,7 +25,7 @@ class pbuf_dec(pgate.pgate): self.height = height # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + pgate.__init__(self, name, height) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/pdriver.py b/compiler/modules/pdriver.py similarity index 98% rename from compiler/pgates/pdriver.py rename to compiler/modules/pdriver.py index 1948b839..a9241af5 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/modules/pdriver.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -import pgate -from vector import vector +from .pgate import * +from base import vector from sram_factory import factory -class pdriver(pgate.pgate): +class pdriver(pgate): """ This instantiates an even or odd number of inverters sized for driving a load. diff --git a/compiler/pgates/pgate.py b/compiler/modules/pgate.py similarity index 98% rename from compiler/pgates/pgate.py rename to compiler/modules/pgate.py index 6a92fa0e..ad61cb68 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/modules/pgate.py @@ -5,20 +5,20 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact -import design +from base import design +from base import vector import debug import math from bisect import bisect_left from tech import layer, drc -from vector import vector from globals import OPTS from tech import cell_properties as cell_props + if cell_props.ptx.bin_spice_models: from tech import nmos_bins, pmos_bins -class pgate(design.design): +class pgate(design): """ This is a module that implements some shared functions for parameterized gates. @@ -113,14 +113,14 @@ class pgate(design.design): left_gate_offset = vector(nmos_gate_pin.lx(), ypos) # Center is completely symmetric. - contact_width = contact.poly_contact.width + contact_width = self.poly_contact.width if position == "center": contact_offset = left_gate_offset \ + vector(0.5 * self.poly_width, 0) elif position == "farleft": contact_offset = left_gate_offset \ - - vector(0.5 * contact.poly_contact.width, 0) + - vector(0.5 * self.poly_contact.width, 0) elif position == "left": contact_offset = left_gate_offset \ - vector(0.5 * contact_width - 0.5 * self.poly_width, 0) @@ -146,7 +146,7 @@ class pgate(design.design): + left_gate_offset.scale(0.5, 0) self.add_rect_center(layer="poly", offset=mid_point, - height=contact.poly_contact.first_layer_width, + height=self.poly_contact.first_layer_width, width=left_gate_offset.x - contact_offset.x) return via @@ -216,6 +216,7 @@ class pgate(design.design): # Offset by half a contact in x and y contact_offset += vector(0.5 * pmos.active_contact.first_layer_width, 0.5 * pmos.active_contact.first_layer_height) + # This over-rides the default one with a custom direction self.nwell_contact = self.add_via_center(layers=layer_stack, offset=contact_offset, implant_type="n", @@ -372,7 +373,7 @@ class pgate(design.design): # It was already set or is left as default (minimum) # Width is determined by well contact and spacing and allowing a supply via between each cell if self.add_wells: - width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width + width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * self.m1_via.width # Height is an input parameter, so it is not recomputed. else: max_active_xoffset = self.find_highest_layer_coords("active").x diff --git a/compiler/pgates/pinv.py b/compiler/modules/pinv.py similarity index 94% rename from compiler/pgates/pinv.py rename to compiler/modules/pinv.py index c458a3f0..a60bed13 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/modules/pinv.py @@ -5,22 +5,21 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact -import pgate import debug +from .pgate import * +from base import vector +from base import logical_effort +from base.utils import round_to_grid +from base.errors import drc_error import operator from tech import drc, parameter, spice -from vector import vector from math import ceil from globals import OPTS -from utils import round_to_grid -import logical_effort from sram_factory import factory -from errors import drc_error from tech import cell_properties as cell_props -class pinv(pgate.pgate): +class pinv(pgate): """ Pinv generates gds of a parametrically sized inverter. The size is specified as the drive size (relative to minimum NMOS) and @@ -89,8 +88,8 @@ class pinv(pgate.pgate): self.nmos_width = self.nmos_size * drc("minwidth_tx") self.pmos_width = self.pmos_size * drc("minwidth_tx") if cell_props.ptx.bin_spice_models: - (self.nmos_width, self.tx_mults) = pgate.pgate.best_bin("nmos", self.nmos_width) - (self.pmos_width, self.tx_mults) = pgate.pgate.best_bin("pmos", self.pmos_width) + (self.nmos_width, self.tx_mults) = pgate.best_bin("nmos", self.nmos_width) + (self.pmos_width, self.tx_mults) = pgate.best_bin("pmos", self.pmos_width) return # Do a quick sanity check and bail if unlikely feasible height @@ -106,8 +105,8 @@ class pinv(pgate.pgate): tx_type="pmos") tx_height = nmos.poly_height + pmos.poly_height # rotated m1 pitch or poly to active spacing - min_channel = max(contact.poly_contact.width + self.m1_space, - contact.poly_contact.width + 2 * self.poly_to_active) + min_channel = max(self.poly_contact.width + self.m1_space, + self.poly_contact.width + 2 * self.poly_to_active) total_height = tx_height + min_channel + 2 * self.top_bottom_space # debug.check(self.height > total_height, @@ -322,12 +321,12 @@ class pinv(pgate.pgate): Input inverted by this stage. """ parasitic_delay = 1 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ diff --git a/compiler/pgates/pinv_dec.py b/compiler/modules/pinv_dec.py similarity index 92% rename from compiler/pgates/pinv_dec.py rename to compiler/modules/pinv_dec.py index b738f5fb..7b378f08 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/modules/pinv_dec.py @@ -5,17 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact -import pinv import debug +from base import vector +from .pinv import pinv from tech import drc, parameter, layer -from vector import vector from globals import OPTS from sram_factory import factory from tech import cell_properties as cell_props -class pinv_dec(pinv.pinv): +class pinv_dec(pinv): """ This is another version of pinv but with layout for the decoder. Other stuff is the same (netlist, sizes, etc.) @@ -78,7 +77,7 @@ class pinv_dec(pinv.pinv): self.add_path("poly", [nmos_gate_pos, pmos_gate_pos]) # Center is completely symmetric. - contact_width = contact.poly_contact.width + contact_width = self.poly_contact.width contact_offset = nmos_gate_pin.lc() \ - vector(self.poly_extend_active + 0.5 * contact_width, 0) via = self.add_via_stack_center(from_layer="poly", @@ -126,7 +125,7 @@ class pinv_dec(pinv.pinv): y_offset = (0.5 * (self.height - self.nmos.width) + self.nmos.width) * 0.9 # offset so that the input contact is over from the left edge by poly spacing - x_offset = self.nmos.active_offset.y + contact.poly_contact.width + self.poly_space + x_offset = self.nmos.active_offset.y + self.poly_contact.width + self.poly_space self.nmos_pos = vector(x_offset, y_offset) self.nmos_inst.place(self.nmos_pos, rotate=270) @@ -192,20 +191,20 @@ class pinv_dec(pinv.pinv): source_pos = self.pmos_inst.get_pin("S").center() contact_pos = vector(source_pos.x, self.height) - self.nwell_contact = self.add_via_center(layers=self.active_stack, - offset=contact_pos, - implant_type="n", - well_type="n") + self.add_via_center(layers=self.active_stack, + offset=contact_pos, + implant_type="n", + well_type="n") self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], to_layer=self.supply_layer) source_pos = self.nmos_inst.get_pin("S").center() contact_pos = vector(source_pos.x, self.height) - self.pwell_contact= self.add_via_center(layers=self.active_stack, - offset=contact_pos, - implant_type="p", - well_type="p") + self.add_via_center(layers=self.active_stack, + offset=contact_pos, + implant_type="p", + well_type="p") self.add_via_stack_center(offset=contact_pos, from_layer=self.active_stack[2], to_layer=self.supply_layer) diff --git a/compiler/pgates/pinvbuf.py b/compiler/modules/pinvbuf.py similarity index 99% rename from compiler/pgates/pinvbuf.py rename to compiler/modules/pinvbuf.py index a48f1cf9..78dca7b5 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/modules/pinvbuf.py @@ -6,12 +6,12 @@ # All rights reserved. # import debug -import pgate -from vector import vector +from .pgate import * +from base import vector from sram_factory import factory from tech import layer -class pinvbuf(pgate.pgate): +class pinvbuf(pgate): """ This is a simple inverter/buffer used for driving loads. It is used in the column decoder for 1:2 decoding and as the clock buffer. diff --git a/compiler/pgates/pnand2.py b/compiler/modules/pnand2.py similarity index 94% rename from compiler/pgates/pnand2.py rename to compiler/modules/pnand2.py index 08b01d4c..9262b2f8 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/modules/pnand2.py @@ -5,17 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import pgate +from .pgate import * import debug from tech import drc, parameter, spice -from vector import vector -import logical_effort +from base import vector +from base import logical_effort from sram_factory import factory -import contact from tech import cell_properties as cell_props -class pnand2(pgate.pgate): +class pnand2(pgate): """ This module generates gds of a parametrically sized 2-input nand. This model use ptx to generate a 2-input nand within a cetrain height. @@ -175,11 +174,11 @@ class pnand2(pgate.pgate): # Top of NMOS drain bottom_pin = self.nmos1_inst.get_pin("D") # active contact metal to poly contact metal spacing - active_contact_to_poly_contact = bottom_pin.uy() + self.route_layer_space + 0.5 * contact.poly_contact.second_layer_height + active_contact_to_poly_contact = bottom_pin.uy() + self.route_layer_space + 0.5 * self.poly_contact.second_layer_height # active diffusion to poly contact spacing # doesn't use nmos uy because that is calculated using offset + poly height active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height - active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + active_to_poly_contact = active_top + self.poly_to_active + 0.5 * self.poly_contact.first_layer_height active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width self.inputA_yoffset = max(active_contact_to_poly_contact, active_to_poly_contact, @@ -193,9 +192,9 @@ class pnand2(pgate.pgate): self.inputB_yoffset = self.inputA_yoffset + 2 * self.m3_pitch # # active contact metal to poly contact metal spacing - # active_contact_to_poly_contact = self.output_yoffset - self.route_layer_space - 0.5 * contact.poly_contact.second_layer_height + # active_contact_to_poly_contact = self.output_yoffset - self.route_layer_space - 0.5 * self.poly_contact.second_layer_height # active_bottom = self.pmos1_inst.by() - # active_to_poly_contact = active_bottom - self.poly_to_active - 0.5 * contact.poly_contact.first_layer_height + # active_to_poly_contact = active_bottom - self.poly_to_active - 0.5 * self.poly_contact.first_layer_height # active_to_poly_contact2 = active_bottom - self.poly_contact_to_gate - 0.5 * self.route_layer_width # self.inputB_yoffset = min(active_contact_to_poly_contact, # active_to_poly_contact, @@ -215,7 +214,7 @@ class pnand2(pgate.pgate): """ Route the Z output """ # One routing track layer below the PMOS contacts - route_layer_offset = 0.5 * contact.poly_contact.second_layer_height + self.route_layer_space + route_layer_offset = 0.5 * self.poly_contact.second_layer_height + self.route_layer_space self.output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset @@ -297,12 +296,12 @@ class pnand2(pgate.pgate): Input inverted by this stage. """ parasitic_delay = 2 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ diff --git a/compiler/pgates/pnand3.py b/compiler/modules/pnand3.py similarity index 96% rename from compiler/pgates/pnand3.py rename to compiler/modules/pnand3.py index 0186907f..31a1b400 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/modules/pnand3.py @@ -5,17 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import pgate +from .pgate import * import debug from tech import drc, parameter, spice -from vector import vector -import logical_effort +from base import vector +from base import logical_effort from sram_factory import factory -import contact from tech import cell_properties as cell_props -class pnand3(pgate.pgate): +class pnand3(pgate): """ This module generates gds of a parametrically sized 2-input nand. This model use ptx to generate a 2-input nand within a cetrain height. @@ -204,17 +203,17 @@ class pnand3(pgate.pgate): """ Route the A and B and C inputs """ # We can use this pitch because the contacts and overlap won't be adjacent - non_contact_pitch = 0.5 * self.m1_width + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + non_contact_pitch = 0.5 * self.m1_width + self.m1_space + 0.5 * self.poly_contact.second_layer_height pmos_drain_bottom = self.pmos1_inst.get_pin("D").by() self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space bottom_pin = self.nmos1_inst.get_pin("D") # active contact metal to poly contact metal spacing - active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * self.poly_contact.second_layer_height # active diffusion to poly contact spacing # doesn't use nmos uy because that is calculated using offset + poly height active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height - active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + active_to_poly_contact = active_top + self.poly_to_active + 0.5 * self.poly_contact.first_layer_height active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width self.inputA_yoffset = max(active_contact_to_poly_contact, active_to_poly_contact, @@ -328,12 +327,12 @@ class pnand3(pgate.pgate): Input inverted by this stage. """ parasitic_delay = 3 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ diff --git a/compiler/pgates/pnand4.py b/compiler/modules/pnand4.py similarity index 96% rename from compiler/pgates/pnand4.py rename to compiler/modules/pnand4.py index eed71eb9..906cb0e8 100644 --- a/compiler/pgates/pnand4.py +++ b/compiler/modules/pnand4.py @@ -5,17 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import pgate +from .pgate import * import debug from tech import drc, parameter, spice -from vector import vector -import logical_effort +from base import vector +from base import logical_effort from sram_factory import factory -import contact from tech import cell_properties as cell_props -class pnand4(pgate.pgate): +class pnand4(pgate): """ This module generates gds of a parametrically sized 4-input nand. This model use ptx to generate a 4-input nand within a cetrain height. @@ -225,11 +224,11 @@ class pnand4(pgate.pgate): bottom_pin = self.nmos1_inst.get_pin("D") # active contact metal to poly contact metal spacing - active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height + active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * self.poly_contact.second_layer_height # active diffusion to poly contact spacing # doesn't use nmos uy because that is calculated using offset + poly height active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height - active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height + active_to_poly_contact = active_top + self.poly_to_active + 0.5 * self.poly_contact.first_layer_height active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width self.inputA_yoffset = max(active_contact_to_poly_contact, active_to_poly_contact, @@ -350,12 +349,12 @@ class pnand4(pgate.pgate): Input inverted by this stage. """ parasitic_delay = 3 - return logical_effort.logical_effort(self.name, - self.size, - self.input_load(), - cout, - parasitic_delay, - not inp_is_rise) + return logical_effort(self.name, + self.size, + self.input_load(), + cout, + parasitic_delay, + not inp_is_rise) def build_graph(self, graph, inst_name, port_nets): """ @@ -384,4 +383,4 @@ class pnand4(pgate.pgate): pmos_drain_c = self.drain_c_(self.pmos_width*self.tx_mults, 1, self.tx_mults) - return nmos_drain_c + pmos_drain_c \ No newline at end of file + return nmos_drain_c + pmos_drain_c diff --git a/compiler/pgates/pnor2.py b/compiler/modules/pnor2.py similarity index 99% rename from compiler/pgates/pnor2.py rename to compiler/modules/pnor2.py index d6384676..35df000f 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/modules/pnor2.py @@ -5,15 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import pgate +from .pgate import * import debug from tech import drc, parameter, spice -from vector import vector +from base import vector from sram_factory import factory from tech import cell_properties as cell_props -class pnor2(pgate.pgate): +class pnor2(pgate): """ This module generates gds of a parametrically sized 2-input nor. This model use ptx to generate a 2-input nor within a cetrain height. diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index a96a556e..26dc3405 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -5,15 +5,15 @@ # from math import log, ceil import debug -import design +from base import design from sram_factory import factory -from vector import vector +from base import vector from tech import layer, drc from globals import OPTS from tech import layer_properties as layer_props -class port_address(design.design): +class port_address(design): """ Create the address port (row decoder and wordline driver).. """ diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 270cfed5..a8f5300f 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -5,17 +5,17 @@ # from tech import drc import debug -import design +from base import design import math from sram_factory import factory from collections import namedtuple -from vector import vector +from base import vector from globals import OPTS from tech import cell_properties from tech import layer_properties as layer_props -class port_data(design.design): +class port_data(design): """ Create the data port (column mux, sense amps, write driver, etc.) for the given port number. Port 0 always has the RBL on the left while port 1 is on the right. diff --git a/compiler/pgates/precharge.py b/compiler/modules/precharge.py similarity index 96% rename from compiler/pgates/precharge.py rename to compiler/modules/precharge.py index 1538e0a5..4a1267e5 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/modules/precharge.py @@ -5,18 +5,17 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact -import design +from base import design import debug -from pgate import pgate +from .pgate import * from tech import parameter, drc -from vector import vector +from base import vector from globals import OPTS from sram_factory import factory from tech import cell_properties as cell_props -class precharge(design.design): +class precharge(design): """ Creates a single precharge cell This module implements the precharge bitline cell used in the design. @@ -178,7 +177,7 @@ class precharge(design.design): pin_offset = self.lower_pmos_inst.get_pin("G").lr() # This is an extra space down for some techs with contact to active spacing contact_space = max(self.poly_space, - self.poly_contact_to_gate) + 0.5 * contact.poly_contact.first_layer_height + self.poly_contact_to_gate) + 0.5 * self.poly_contact.first_layer_height offset = pin_offset - vector(0, contact_space) self.add_via_stack_center(from_layer="poly", to_layer=self.en_layer, @@ -198,7 +197,7 @@ class precharge(design.design): # adds the contact from active to metal1 offset_height = self.upper_pmos1_inst.uy() + \ - contact.active_contact.height + \ + self.active_contact.height + \ self.nwell_extend_active self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \ vector(0, offset_height) @@ -210,7 +209,7 @@ class precharge(design.design): to_layer=self.bitline_layer, offset=self.well_contact_pos) - self.height = self.well_contact_pos.y + contact.active_contact.height + self.m1_space + self.height = self.well_contact_pos.y + self.active_contact.height + self.m1_space # nwell should span the whole design since it is pmos only self.add_rect(layer="nwell", diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 372a5629..3c7ab681 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -5,14 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug -from vector import vector +from base import vector from sram_factory import factory from globals import OPTS -class precharge_array(design.design): +class precharge_array(design): """ Dynamically generated precharge array of all bitlines. Cols is number of bit line columns, height is the height of the bit-cell array. diff --git a/compiler/pgates/ptristate_inv.py b/compiler/modules/ptristate_inv.py similarity index 89% rename from compiler/pgates/ptristate_inv.py rename to compiler/modules/ptristate_inv.py index b37c36ae..583b68ea 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/modules/ptristate_inv.py @@ -5,15 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import contact -import pgate +from .pgate import * import debug from tech import drc, parameter, spice -from vector import vector +from base import vector from sram_factory import factory -class ptristate_inv(pgate.pgate): +class ptristate_inv(pgate): """ ptristate generates gds of a parametrically sized tristate inverter. There is some flexibility in the size, but we do not allow multiple fingers @@ -131,8 +130,8 @@ class ptristate_inv(pgate.pgate): """ pmos_yoff = self.height - self.pmos.active_height \ - - self.top_bottom_space - 0.5 * contact.active_contact.height - nmos_yoff = self.top_bottom_space + 0.5 * contact.active_contact.height + - self.top_bottom_space - 0.5 * self.active_contact.height + nmos_yoff = self.top_bottom_space + 0.5 * self.active_contact.height # Tristate transistors pmos1_pos = vector(self.pmos.active_offset.x, pmos_yoff) @@ -188,16 +187,16 @@ class ptristate_inv(pgate.pgate): drain_pos = self.nmos1_inst.get_pin("S").center() vdd_pos = self.get_pin("vdd").center() - self.nwell_contact = self.add_via_center(layers=layer_stack, - offset=vector(drain_pos.x, vdd_pos.y), - implant_type="n", - well_type="n") + self.add_via_center(layers=layer_stack, + offset=vector(drain_pos.x, vdd_pos.y), + implant_type="n", + well_type="n") gnd_pos = self.get_pin("gnd").center() - self.pwell_contact = self.add_via_center(layers=layer_stack, - offset=vector(drain_pos.x, gnd_pos.y), - implant_type="p", - well_type="p") + self.add_via_center(layers=layer_stack, + offset=vector(drain_pos.x, gnd_pos.y), + implant_type="p", + well_type="p") def connect_rails(self): """ Connect the nmos and pmos to its respective power rails """ diff --git a/compiler/pgates/ptx.py b/compiler/modules/ptx.py similarity index 97% rename from compiler/pgates/ptx.py rename to compiler/modules/ptx.py index e49df518..d1bd13c8 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/modules/ptx.py @@ -5,18 +5,17 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design import debug +from base import design +from base import logical_effort +from base import vector from tech import layer, drc, spice -from vector import vector from sram_factory import factory -import contact -import logical_effort from globals import OPTS from tech import cell_properties as cell_props -class ptx(design.design): +class ptx(design): """ This module generates gds and spice of a parametrically NMOS or PMOS sized transistor. Pins are accessed as D, G, S, B. Width is @@ -198,12 +197,12 @@ class ptx(design.design): # This is the extra poly spacing due to the poly contact to poly contact pitch # of contacted gates - extra_poly_contact_width = contact.poly_contact.width - self.poly_width + extra_poly_contact_width = self.poly_contact.width - self.poly_width # This is the spacing between S/D contacts # This is the spacing between the poly gates self.min_poly_pitch = self.poly_space + self.poly_width - self.contacted_poly_pitch = self.poly_space + contact.poly_contact.width + self.contacted_poly_pitch = self.poly_space + self.poly_contact.width self.contact_pitch = 2 * self.active_contact_to_gate + self.poly_width + self.contact_width self.poly_pitch = max(self.min_poly_pitch, self.contacted_poly_pitch, @@ -487,11 +486,11 @@ class ptx(design.design): # FIXME: Using the same definition as the pinv.py. parasitic_delay = 1 size = self.mults * self.tx_width / drc("minwidth_tx") - return logical_effort.logical_effort(self.name, - size, - self.input_load(), - cout, - parasitic_delay) + return logical_effort(self.name, + size, + self.input_load(), + cout, + parasitic_delay) def input_load(self): """ diff --git a/compiler/pgates/pwrite_driver.py b/compiler/modules/pwrite_driver.py similarity index 99% rename from compiler/pgates/pwrite_driver.py rename to compiler/modules/pwrite_driver.py index 103e902b..9af6c78f 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/modules/pwrite_driver.py @@ -5,15 +5,15 @@ #(acting for and on behalf of Oklahoma State University) #All rights reserved. # -import design +from base import design from tech import parameter import debug -from vector import vector +from base import vector from globals import OPTS from sram_factory import factory -class pwrite_driver(design.design): +class pwrite_driver(design): """ The pwrite_driver is two tristate inverters that drive the bitlines. The data input is first inverted before one tristate. diff --git a/compiler/bitcells/replica_bitcell_1port.py b/compiler/modules/replica_bitcell_1port.py similarity index 89% rename from compiler/bitcells/replica_bitcell_1port.py rename to compiler/modules/replica_bitcell_1port.py index 191ba4a7..f33fc2f9 100644 --- a/compiler/bitcells/replica_bitcell_1port.py +++ b/compiler/modules/replica_bitcell_1port.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import bitcell_base +from .bitcell_base import bitcell_base from tech import cell_properties as props from tech import parameter, drc -import logical_effort +from base import logical_effort -class replica_bitcell_1port(bitcell_base.bitcell_base): +class replica_bitcell_1port(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It @@ -28,7 +28,7 @@ class replica_bitcell_1port(bitcell_base.bitcell_base): size = 0.5 # This accounts for bitline being drained thought the access TX and internal node cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file. read_port_load = 0.5 # min size NMOS gate load - return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) + return logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) def input_load(self): """Return the relative capacitance of the access transistor gates""" @@ -52,4 +52,4 @@ class replica_bitcell_1port(bitcell_base.bitcell_base): def is_non_inverting(self): """Return input to output polarity for module""" - return False \ No newline at end of file + return False diff --git a/compiler/bitcells/replica_bitcell_2port.py b/compiler/modules/replica_bitcell_2port.py similarity index 90% rename from compiler/bitcells/replica_bitcell_2port.py rename to compiler/modules/replica_bitcell_2port.py index 8d113805..64c3c4e1 100644 --- a/compiler/bitcells/replica_bitcell_2port.py +++ b/compiler/modules/replica_bitcell_2port.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import bitcell_base +from .bitcell_base import bitcell_base from tech import cell_properties as props from tech import parameter, drc -import logical_effort +from base import logical_effort -class replica_bitcell_2port(bitcell_base.bitcell_base): +class replica_bitcell_2port(bitcell_base): """ A single bit cell which is forced to store a 0. This module implements the single memory cell used in the design. It @@ -28,7 +28,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base): size = 0.5 # This accounts for bitline being drained thought the access TX and internal node cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file. read_port_load = 0.5 # min size NMOS gate load - return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) + return logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) def input_load(self): """Return the relative capacitance of the access transistor gates""" @@ -53,4 +53,4 @@ class replica_bitcell_2port(bitcell_base.bitcell_base): def is_non_inverting(self): """Return input to output polarity for module""" - return False \ No newline at end of file + return False diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 92a0358b..609aa566 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -5,12 +5,11 @@ # import debug -from bitcell_base_array import bitcell_base_array -from pbitcell import pbitcell -from contact import contact -from tech import drc, spice, preferred_directions +from base import vector +from base import contact +from .bitcell_base_array import bitcell_base_array +from tech import drc, spice from tech import cell_properties as props -from vector import vector from globals import OPTS from sram_factory import factory diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 43a3cda3..5f59c016 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -4,9 +4,9 @@ # All rights reserved. # import debug -from bitcell_base_array import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from sram_factory import factory -from vector import vector +from base import vector from globals import OPTS from tech import layer_properties as layer_props diff --git a/compiler/bitcells/replica_pbitcell.py b/compiler/modules/replica_pbitcell.py similarity index 95% rename from compiler/bitcells/replica_pbitcell.py rename to compiler/modules/replica_pbitcell.py index bf2fa032..54fda10a 100644 --- a/compiler/bitcells/replica_pbitcell.py +++ b/compiler/modules/replica_pbitcell.py @@ -6,13 +6,13 @@ # All rights reserved. # import debug -import design -from vector import vector +from base import design +from base import vector from globals import OPTS from sram_factory import factory -class replica_pbitcell(design.design): +class replica_pbitcell(design): """ Creates a replica bitcell using pbitcell """ @@ -25,7 +25,7 @@ class replica_pbitcell(design.design): self.num_r_ports = OPTS.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - design.design.__init__(self, name, cell_name) + design.__init__(self, name, cell_name) debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports)) diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index 8f092dc4..61b736b3 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -3,7 +3,7 @@ # Copyright (c) 2016-2021 Regents of the University of California # All rights reserved. # -from bitcell_base_array import bitcell_base_array +from .bitcell_base_array import bitcell_base_array from sram_factory import factory from globals import OPTS diff --git a/compiler/bitcells/row_cap_bitcell_1port.py b/compiler/modules/row_cap_bitcell_1port.py similarity index 87% rename from compiler/bitcells/row_cap_bitcell_1port.py rename to compiler/modules/row_cap_bitcell_1port.py index 9fb1f813..82849000 100644 --- a/compiler/bitcells/row_cap_bitcell_1port.py +++ b/compiler/modules/row_cap_bitcell_1port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class row_cap_bitcell_1port(bitcell_base.bitcell_base): +class row_cap_bitcell_1port(bitcell_base): """ Row end cap cell. """ diff --git a/compiler/bitcells/row_cap_bitcell_2port.py b/compiler/modules/row_cap_bitcell_2port.py similarity index 87% rename from compiler/bitcells/row_cap_bitcell_2port.py rename to compiler/modules/row_cap_bitcell_2port.py index 0c2989b0..771e9043 100644 --- a/compiler/bitcells/row_cap_bitcell_2port.py +++ b/compiler/modules/row_cap_bitcell_2port.py @@ -7,10 +7,10 @@ # import debug from tech import cell_properties as props -import bitcell_base +from .bitcell_base import bitcell_base -class row_cap_bitcell_2port(bitcell_base.bitcell_base): +class row_cap_bitcell_2port(bitcell_base): """ Row end cap cell. """ diff --git a/compiler/custom/sense_amp.py b/compiler/modules/sense_amp.py similarity index 96% rename from compiler/custom/sense_amp.py rename to compiler/modules/sense_amp.py index 51328a54..3440e5a7 100644 --- a/compiler/custom/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -5,14 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug from tech import parameter, drc, spice from tech import cell_properties as props -import logical_effort +from base import logical_effort -class sense_amp(design.design): +class sense_amp(design): """ This module implements the single sense amp cell used in the design. It is a hand-made cell, so the layout and netlist should be available in @@ -55,7 +55,7 @@ class sense_amp(design.design): cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"]) / drc("minwidth_tx") sa_size = parameter["sa_inv_nmos_size"] / drc("minwidth_tx") cc_inv_cin = cin - return logical_effort.logical_effort('column_mux', sa_size, cin, load + cc_inv_cin, parasitic_delay, False) + return logical_effort('column_mux', sa_size, cin, load + cc_inv_cin, parasitic_delay, False) def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index daabf8df..3e98a517 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -5,15 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design -from vector import vector +from base import design +from base import vector from sram_factory import factory from tech import cell_properties import debug from globals import OPTS -class sense_amp_array(design.design): +class sense_amp_array(design): """ Array of sense amplifiers to read the bitlines through the column mux. Dynamically generated sense amp array for all bitlines. diff --git a/compiler/sram/sram.py b/compiler/modules/sram.py similarity index 95% rename from compiler/sram/sram.py rename to compiler/modules/sram.py index b656f547..70d8afce 100644 --- a/compiler/sram/sram.py +++ b/compiler/modules/sram.py @@ -8,7 +8,6 @@ import datetime import os import debug -import verify from characterizer import functional from globals import OPTS, print_time import shutil @@ -27,7 +26,7 @@ class sram(): # reset the static duplicate name checker for unit tests # in case we create more than one SRAM - from design import design + from base import design design.name_map=[] debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size, @@ -38,9 +37,9 @@ class sram(): self.name = name if self.num_banks == 1: - from sram_1bank import sram_1bank as sram + from .sram_1bank import sram_1bank as sram elif self.num_banks == 2: - from sram_2bank import sram_2bank as sram + from .sram_2bank import sram_2bank as sram else: debug.error("Invalid number of banks.", -1) @@ -79,6 +78,10 @@ class sram(): def save(self): """ Save all the output files while reporting time to do it as well. """ + # Import this at the last minute so that the proper tech file + # is loaded and the right tools are selected + import verify + # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" @@ -155,7 +158,7 @@ class sram(): # Write the datasheet start_time = datetime.datetime.now() - from datasheet_gen import datasheet_gen + from datasheet import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) diff --git a/compiler/sram/sram_1bank.py b/compiler/modules/sram_1bank.py similarity index 99% rename from compiler/sram/sram_1bank.py rename to compiler/modules/sram_1bank.py index a410e04a..a26ea7e8 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -5,11 +5,10 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from vector import vector -from sram_base import sram_base -from contact import m2_via -from channel_route import channel_route -from router_tech import router_tech +from base import vector +from .sram_base import sram_base +from base import channel_route +from router import router_tech from globals import OPTS @@ -537,7 +536,7 @@ class sram_1bank(sram_base): # so make the wire as wide as the contacts self.add_path("m2", [mid_pos, clk_steiner_pos], - width=max(m2_via.width, m2_via.height)) + width=max(self.m2_via.width, self.m2_via.height)) self.add_wire(self.m2_stack[::-1], [data_dff_clk_pos, mid_pos, clk_steiner_pos]) diff --git a/compiler/sram/sram_2bank.py b/compiler/modules/sram_2bank.py similarity index 98% rename from compiler/sram/sram_2bank.py rename to compiler/modules/sram_2bank.py index 421641ac..69ecb496 100644 --- a/compiler/sram/sram_2bank.py +++ b/compiler/modules/sram_2bank.py @@ -11,13 +11,13 @@ import debug from math import log,sqrt,ceil import datetime import getpass -from vector import vector +from base import vector from globals import OPTS, print_time -from sram_base import sram_base -from bank import bank -from dff_buf_array import dff_buf_array -from dff_array import dff_array +from .sram_base import sram_base +from modules import bank +from modules import dff_buf_array +from modules import dff_array class sram_2bank(sram_base): """ diff --git a/compiler/sram/sram_base.py b/compiler/modules/sram_base.py similarity index 98% rename from compiler/sram/sram_base.py rename to compiler/modules/sram_base.py index 6feda56f..722a649d 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/modules/sram_base.py @@ -7,13 +7,13 @@ # import datetime import debug -from math import log, ceil -from importlib import reload -from vector import vector from globals import OPTS, print_time -from design import design -from verilog import verilog -from lef import lef +from math import log, ceil +import importlib +from base.vector import vector +from base.design import design +from base.verilog import verilog +from base.lef import lef from sram_factory import factory from tech import spice @@ -248,9 +248,9 @@ class sram_base(design, verilog, lef): # Do not route the power supply (leave as must-connect pins) return elif OPTS.route_supplies == "grid": - from supply_grid_router import supply_grid_router as router + from router import supply_grid_router as router else: - from supply_tree_router import supply_tree_router as router + from router import supply_tree_router as router rtr=router(layers=self.supply_stack, design=self, @@ -364,7 +364,7 @@ class sram_base(design, verilog, lef): for bit in range(self.num_spare_cols): pins_to_route.append("spare_wen{0}[{1}]".format(port, bit)) - from signal_escape_router import signal_escape_router as router + from router import signal_escape_router as router rtr=router(layers=self.m3_stack, design=self, bbox=bbox) @@ -500,7 +500,7 @@ class sram_base(design, verilog, lef): self.bank_count = 0 - c = reload(__import__(OPTS.control_logic)) + c = importlib.import_module("modules." + OPTS.control_logic) self.mod_control_logic = getattr(c, OPTS.control_logic) # Create the control logic module for each port type diff --git a/compiler/sram/sram_config.py b/compiler/modules/sram_config.py similarity index 100% rename from compiler/sram/sram_config.py rename to compiler/modules/sram_config.py diff --git a/compiler/custom/tri_gate.py b/compiler/modules/tri_gate.py similarity index 96% rename from compiler/custom/tri_gate.py rename to compiler/modules/tri_gate.py index f0c0afeb..c5d65d57 100644 --- a/compiler/custom/tri_gate.py +++ b/compiler/modules/tri_gate.py @@ -6,11 +6,11 @@ # All rights reserved. # import debug -import design +from base import design from tech import spice -class tri_gate(design.design): +class tri_gate(design): """ This module implements the tri gate cell used in the design forS bit-line isolation. It is a hand-made cell, so the layout and diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index b1e9eebe..984d8039 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -7,12 +7,12 @@ # import debug from tech import drc -import design -from vector import vector +from base import design +from base import vector from sram_factory import factory from globals import OPTS -class tri_gate_array(design.design): +class tri_gate_array(design): """ Dynamically generated tri gate array of all bitlines. words_per_row """ diff --git a/compiler/modules/wordline_buffer_array.py b/compiler/modules/wordline_buffer_array.py index 9c74b79d..d624d5db 100644 --- a/compiler/modules/wordline_buffer_array.py +++ b/compiler/modules/wordline_buffer_array.py @@ -6,21 +6,21 @@ # All rights reserved. # import debug -import design +from base import design from tech import layer -from vector import vector +from base import vector from sram_factory import factory from globals import OPTS from tech import layer_properties as layer_props -class wordline_buffer_array(design.design): +class wordline_buffer_array(design): """ Creates a Wordline Buffer/Inverter array """ def __init__(self, name, rows, cols): - design.design.__init__(self, name) + design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) diff --git a/compiler/pgates/wordline_driver.py b/compiler/modules/wordline_driver.py similarity index 98% rename from compiler/pgates/wordline_driver.py rename to compiler/modules/wordline_driver.py index d0f72c23..e8fd8901 100644 --- a/compiler/pgates/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -6,15 +6,15 @@ # All rights reserved. # import debug -from vector import vector -import design +from base import vector +from base import design from sram_factory import factory from globals import OPTS from tech import layer from tech import layer_properties as layer_props -class wordline_driver(design.design): +class wordline_driver(design): """ This is an AND (or NAND) with configurable drive strength to drive the wordlines. It is matched to the bitcell height. diff --git a/compiler/modules/wordline_driver_array.py b/compiler/modules/wordline_driver_array.py index 63c39a7c..8a1e100a 100644 --- a/compiler/modules/wordline_driver_array.py +++ b/compiler/modules/wordline_driver_array.py @@ -6,15 +6,15 @@ # All rights reserved. # import debug -import design +from base import design from tech import drc, layer -from vector import vector +from base import vector from sram_factory import factory from globals import OPTS from tech import layer_properties as layer_props -class wordline_driver_array(design.design): +class wordline_driver_array(design): """ Creates a Wordline Driver Generates the wordline-driver to drive the bitcell diff --git a/compiler/custom/write_driver.py b/compiler/modules/write_driver.py similarity index 96% rename from compiler/custom/write_driver.py rename to compiler/modules/write_driver.py index 6d5c4018..00afa0ee 100644 --- a/compiler/custom/write_driver.py +++ b/compiler/modules/write_driver.py @@ -6,11 +6,11 @@ # All rights reserved. # import debug -import design +from base import design from tech import cell_properties as props -class write_driver(design.design): +class write_driver(design): """ Tristate write driver to be active during write operations only. This module implements the write driver cell used in the design. It diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 3262e555..ee3d3c2f 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -5,16 +5,16 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug import math from tech import drc from sram_factory import factory -from vector import vector +from base import vector from globals import OPTS -class write_driver_array(design.design): +class write_driver_array(design): """ Array of tristate drivers to write to the bitlines through the column mux. Dynamically generated write driver array of all bitlines. diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index f7818e12..f3e7e9bc 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -5,15 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import design +from base import design import debug import math from sram_factory import factory -from vector import vector +from base import vector from globals import OPTS -class write_mask_and_array(design.design): +class write_mask_and_array(design): """ Array of AND gates to turn write mask signal on only when w_en is on. The write mask AND array goes between the write driver array and the sense amp array. diff --git a/compiler/openram.py b/compiler/openram.py index 8ce6ae1e..fbbf4466 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -47,7 +47,7 @@ g.print_time("Start", start_time) # Output info about this run g.report_status() -from sram_config import sram_config +from modules import sram_config # Configure the SRAM organization @@ -73,7 +73,7 @@ for path in output_files: debug.print_raw(path) -from sram import sram +from modules import sram s = sram(name=OPTS.output_name, sram_config=c) diff --git a/compiler/router/__init__.py b/compiler/router/__init__.py new file mode 100644 index 00000000..a4496fb0 --- /dev/null +++ b/compiler/router/__init__.py @@ -0,0 +1,5 @@ +from .router import * +from .signal_escape_router import * +from .signal_router import * +from .supply_grid_router import * +from .supply_tree_router import * diff --git a/compiler/router/direction.py b/compiler/router/direction.py index c13abdd3..a7eeb727 100644 --- a/compiler/router/direction.py +++ b/compiler/router/direction.py @@ -6,7 +6,7 @@ # All rights reserved. # from enum import Enum -from vector3d import vector3d +from base.vector3d import vector3d import debug diff --git a/compiler/router/grid.py b/compiler/router/grid.py index a366ebe0..8fd1de72 100644 --- a/compiler/router/grid.py +++ b/compiler/router/grid.py @@ -6,8 +6,8 @@ # All rights reserved. # import debug -from vector3d import vector3d -from grid_cell import grid_cell +from base.vector3d import vector3d +from .grid_cell import grid_cell class grid: diff --git a/compiler/router/grid_path.py b/compiler/router/grid_path.py index d47b2677..1c7c576a 100644 --- a/compiler/router/grid_path.py +++ b/compiler/router/grid_path.py @@ -5,10 +5,10 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from vector3d import vector3d from itertools import tee -from grid import grid -from direction import direction +from base.vector3d import vector3d +from .grid import grid +from .direction import direction class grid_path: diff --git a/compiler/router/grid_utils.py b/compiler/router/grid_utils.py index 1085f5c7..0bf954a3 100644 --- a/compiler/router/grid_utils.py +++ b/compiler/router/grid_utils.py @@ -10,8 +10,8 @@ Some utility functions for sets of grid cells. """ import math -from direction import direction -from vector3d import vector3d +from .direction import direction +from base.vector3d import vector3d def increment_set(curset, direct): diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index d67200d5..0819d62a 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -5,11 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from direction import direction -from pin_layout import pin_layout -from vector import vector -from vector3d import vector3d import debug +from base.vector import vector +from base.vector3d import vector3d +from base.pin_layout import pin_layout +from .direction import direction class pin_group: diff --git a/compiler/router/router.py b/compiler/router/router.py index 2e5236ea..756047e9 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -8,18 +8,18 @@ import itertools import math -import gdsMill +from datetime import datetime +from gdsMill import gdsMill +import debug +from globals import OPTS, print_time from tech import drc, GDS from tech import layer as techlayer -import debug -from router_tech import router_tech -from pin_layout import pin_layout -from pin_group import pin_group -from vector import vector -from vector3d import vector3d -from globals import OPTS, print_time -import grid_utils -from datetime import datetime +from base.vector import vector +from base.vector3d import vector3d +from base.pin_layout import pin_layout +from .router_tech import router_tech +from .pin_group import pin_group +from . import grid_utils class router(router_tech): diff --git a/compiler/router/router_tech.py b/compiler/router/router_tech.py index 6cbbd422..22f1fd15 100644 --- a/compiler/router/router_tech.py +++ b/compiler/router/router_tech.py @@ -6,8 +6,8 @@ # All rights reserved. # from tech import drc, layer, preferred_directions -from contact import contact -from vector import vector +from base.contact import contact +from base.vector import vector import debug import math diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py index d727e900..11d689c7 100644 --- a/compiler/router/signal_escape_router.py +++ b/compiler/router/signal_escape_router.py @@ -5,11 +5,11 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from datetime import datetime import debug from globals import print_time -from router import router -from datetime import datetime -from signal_grid import signal_grid +from .router import router +from .signal_grid import signal_grid class signal_escape_router(router): diff --git a/compiler/router/signal_grid.py b/compiler/router/signal_grid.py index 3d8c69eb..f6ea31f5 100644 --- a/compiler/router/signal_grid.py +++ b/compiler/router/signal_grid.py @@ -8,10 +8,9 @@ import debug from heapq import heappush,heappop from copy import deepcopy - -from grid import grid -from grid_path import grid_path -from vector3d import vector3d +from base.vector3d import vector3d +from .grid import grid +from .grid_path import grid_path class signal_grid(grid): diff --git a/compiler/router/supply_grid.py b/compiler/router/supply_grid.py index a5f2248f..0ed66c7a 100644 --- a/compiler/router/supply_grid.py +++ b/compiler/router/supply_grid.py @@ -5,8 +5,8 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -from signal_grid import signal_grid -from grid_path import grid_path +from .signal_grid import signal_grid +from .grid_path import grid_path class supply_grid(signal_grid): diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index 06831299..e592e02d 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -5,14 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +from datetime import datetime import debug from globals import print_time -from vector3d import vector3d -from router import router -from direction import direction -from datetime import datetime -from supply_grid import supply_grid -import grid_utils +from base.vector3d import vector3d +from .router import router +from .direction import direction +from .supply_grid import supply_grid +from . import grid_utils class supply_grid_router(router): diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index a018a129..80a386e0 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -5,14 +5,14 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug -from globals import print_time -from router import router from datetime import datetime -import grid_utils from scipy.sparse import csr_matrix from scipy.sparse.csgraph import minimum_spanning_tree -from signal_grid import signal_grid +import debug +from globals import print_time +from .router import router +from . import grid_utils +from .signal_grid import signal_grid class supply_tree_router(router): diff --git a/compiler/sram/__init__.py b/compiler/sram/__init__.py new file mode 100644 index 00000000..93bb0cbb --- /dev/null +++ b/compiler/sram/__init__.py @@ -0,0 +1,5 @@ +from .sram_1bank import * +from .sram_2bank import * +from .sram_base import * +from .sram_config import * +from .sram import * diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 1fd145b7..0ebb6865 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -6,6 +6,7 @@ # All rights reserved. # from globals import OPTS +import importlib class sram_factory: @@ -101,10 +102,18 @@ class sram_factory: # Load a cached version from previous usage mod = self.modules[real_module_type] except KeyError: - # Dynamically load the module - import importlib - c = importlib.reload(__import__(real_module_type)) + try: + # Dynamically load the module + if real_module_type == "contact": + c = importlib.import_module("base.contact") + else: + c = importlib.import_module("modules."+real_module_type) + except ModuleNotFoundError: + # Check if it is a technology specific module + c = importlib.import_module("custom."+real_module_type) + mod = getattr(c, real_module_type) + self.modules[real_module_type] = mod self.module_indices[real_module_type] = 0 self.objects[real_module_type] = [] diff --git a/compiler/tests/00_code_format_check_test.py b/compiler/tests/00_code_format_check_test.py index 6851f6a1..7fb5862d 100755 --- a/compiler/tests/00_code_format_check_test.py +++ b/compiler/tests/00_code_format_check_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals import debug diff --git a/compiler/tests/01_library_test.py b/compiler/tests/01_library_test.py index 53151658..35d9eca2 100755 --- a/compiler/tests/01_library_test.py +++ b/compiler/tests/01_library_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index c39c4c8b..34c96063 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index c16794de..a08edad7 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -19,9 +19,9 @@ class path_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import wire_path + from base import wire_path import tech - import design + from base import design min_space = 2 * tech.drc["minwidth_m1"] layer_stack = ("m1") @@ -32,8 +32,8 @@ class path_test(openram_test): [4 * min_space, 3 * min_space ], [0, 3 * min_space ], [0, 6 * min_space ]] - w = design.design("path_test0") - wire_path.wire_path(w,layer_stack, position_list) + w = design("path_test0") + wire_path(w,layer_stack, position_list) self.local_drc_check(w) @@ -49,8 +49,8 @@ class path_test(openram_test): [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x+min_space, y+min_space] for x,y in old_position_list] - w = design.design("path_test1") - wire_path.wire_path(w,layer_stack, position_list) + w = design("path_test1") + wire_path(w,layer_stack, position_list) self.local_drc_check(w) min_space = 2 * tech.drc["minwidth_m2"] @@ -65,8 +65,8 @@ class path_test(openram_test): [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x-min_space, y-min_space] for x,y in old_position_list] - w = design.design("path_test2") - wire_path.wire_path(w, layer_stack, position_list) + w = design("path_test2") + wire_path(w, layer_stack, position_list) self.local_drc_check(w) min_space = 2 * tech.drc["minwidth_m3"] @@ -82,8 +82,8 @@ class path_test(openram_test): [-1 * min_space, 0]] # run on the reverse list position_list.reverse() - w = design.design("path_test3") - wire_path.wire_path(w, layer_stack, position_list) + w = design("path_test3") + wire_path(w, layer_stack, position_list) self.local_drc_check(w) globals.end_openram() diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 98cc1a5e..2ebf7d45 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 77bacea2..53922c9b 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index e5ed6894..a4e18aa2 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 29e209e3..b4776456 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 1c8160e4..c1c2184b 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 408bffbc..fcc843bb 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_ptx_no_contacts_test.py b/compiler/tests/03_ptx_no_contacts_test.py index 745e4f0b..36b53d8f 100755 --- a/compiler/tests/03_ptx_no_contacts_test.py +++ b/compiler/tests/03_ptx_no_contacts_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 1de6a7d5..8906e1cf 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys import os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals @@ -19,9 +19,9 @@ class wire_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import wire + from base import wire import tech - import design + from base import design layer_stacks = [tech.poly_stack] + tech.beol_stacks @@ -46,8 +46,8 @@ class wire_test(openram_test): [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x - min_space, y - min_space] for x, y in position_list] - w = design.design("wire_test_{}".format("_".join(layer_stack))) - wire.wire(w, layer_stack, position_list) + w = design("wire_test_{}".format("_".join(layer_stack))) + wire(w, layer_stack, position_list) self.local_drc_check(w) globals.end_openram() diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py index 69bdd676..93ad6d41 100755 --- a/compiler/tests/04_and2_dec_test.py +++ b/compiler/tests/04_and2_dec_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py index bcf4e85b..6b6389e3 100755 --- a/compiler/tests/04_and3_dec_test.py +++ b/compiler/tests/04_and3_dec_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index 4dbb2613..c849e6d6 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_column_mux_1rw_1r_test.py b/compiler/tests/04_column_mux_1rw_1r_test.py index 8e45d6c5..56b4301a 100755 --- a/compiler/tests/04_column_mux_1rw_1r_test.py +++ b/compiler/tests/04_column_mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_column_mux_pbitcell_test.py b/compiler/tests/04_column_mux_pbitcell_test.py index 8ee985d5..4ce02164 100755 --- a/compiler/tests/04_column_mux_pbitcell_test.py +++ b/compiler/tests/04_column_mux_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_column_mux_test.py b/compiler/tests/04_column_mux_test.py index 4254560a..78770b5b 100755 --- a/compiler/tests/04_column_mux_test.py +++ b/compiler/tests/04_column_mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_dff_buf_test.py b/compiler/tests/04_dff_buf_test.py index 5064e297..c8d2842e 100755 --- a/compiler/tests/04_dff_buf_test.py +++ b/compiler/tests/04_dff_buf_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index ad70820b..0d955283 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -20,7 +20,7 @@ class replica_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import dummy_pbitcell + from modules import dummy_pbitcell OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 @@ -29,7 +29,7 @@ class replica_pbitcell_test(openram_test): factory.reset() debug.info(2, "Checking dummy bitcell using pbitcell (small cell)") - tx = dummy_pbitcell.dummy_pbitcell(name="rpbc") + tx = dummy_pbitcell(name="rpbc") self.local_check(tx) OPTS.num_rw_ports = 1 @@ -38,7 +38,7 @@ class replica_pbitcell_test(openram_test): factory.reset() debug.info(2, "Checking dummy bitcell using pbitcell (large cell)") - tx = dummy_pbitcell.dummy_pbitcell(name="rpbc") + tx = dummy_pbitcell(name="rpbc") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index de08a0e1..d1e9f6ff 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -23,10 +23,10 @@ class pand2_test(openram_test): global verify import verify - import pand2 + from modules import pand2 debug.info(2, "Testing pand2 gate 4x") - a = pand2.pand2(name="pand2x4", size=4) + a = pand2(name="pand2x4", size=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index e27c1050..3b49e3a1 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -23,10 +23,10 @@ class pand3_test(openram_test): global verify import verify - import pand3 + from modules import pand3 debug.info(2, "Testing pand3 gate 4x") - a = pand3.pand3(name="pand3x4", size=4) + a = pand3(name="pand3x4", size=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pand4_test.py b/compiler/tests/04_pand4_test.py index cd1a4495..2c5f5878 100755 --- a/compiler/tests/04_pand4_test.py +++ b/compiler/tests/04_pand4_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -23,10 +23,10 @@ class pand4_test(openram_test): global verify import verify - import pand4 + from modules import pand4 debug.info(2, "Testing pand4 gate 4x") - a = pand4.pand4(name="pand4x4", size=4) + a = pand4(name="pand4x4", size=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index fa9c05c1..119afc41 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug diff --git a/compiler/tests/04_pbuf_dec_8x_test.py b/compiler/tests/04_pbuf_dec_8x_test.py index c8086653..823f9bcc 100755 --- a/compiler/tests/04_pbuf_dec_8x_test.py +++ b/compiler/tests/04_pbuf_dec_8x_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 1ee571b3..72a5f2ff 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index fb95fb31..71ad80cd 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinv_100x_test.py b/compiler/tests/04_pinv_100x_test.py index c9c23440..0d86e0a8 100755 --- a/compiler/tests/04_pinv_100x_test.py +++ b/compiler/tests/04_pinv_100x_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 5b8ea70c..8151bf41 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index a8cc1b46..9ecbc3aa 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index d1a0abf3..f6f4ca04 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index aed3bb6e..0ae30973 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py index 14f046cd..7aee5219 100755 --- a/compiler/tests/04_pinv_dec_1x_test.py +++ b/compiler/tests/04_pinv_dec_1x_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 859eed61..4f227181 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 6a8b1f4c..053e343c 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index a1142b55..a934f698 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pnand4_test.py b/compiler/tests/04_pnand4_test.py index a47ff7d2..bceff7f9 100755 --- a/compiler/tests/04_pnand4_test.py +++ b/compiler/tests/04_pnand4_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 117044ce..a68a7190 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py index a5163e69..026deaee 100755 --- a/compiler/tests/04_precharge_1rw_1r_test.py +++ b/compiler/tests/04_precharge_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py index 74e2fe54..ae9740fb 100755 --- a/compiler/tests/04_precharge_pbitcell_test.py +++ b/compiler/tests/04_precharge_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 65b9a5f9..3d1d3832 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_pwrite_driver_test.py b/compiler/tests/04_pwrite_driver_test.py index 4f7c6ca3..7d2d525b 100755 --- a/compiler/tests/04_pwrite_driver_test.py +++ b/compiler/tests/04_pwrite_driver_test.py @@ -10,7 +10,7 @@ import unittest from testutils import header, openram_test import sys import os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 8e3ae17e..5b4e7271 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -20,7 +20,7 @@ class replica_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import replica_pbitcell + from modules import replica_pbitcell OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 @@ -29,7 +29,7 @@ class replica_pbitcell_test(openram_test): factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (small cell)") - tx = replica_pbitcell.replica_pbitcell(name="rpbc") + tx = replica_pbitcell(name="rpbc") self.local_check(tx) OPTS.num_rw_ports = 1 @@ -38,7 +38,7 @@ class replica_pbitcell_test(openram_test): factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (large cell)") - tx = replica_pbitcell.replica_pbitcell(name="rpbc") + tx = replica_pbitcell(name="rpbc") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py index 3713ff02..c71e3190 100755 --- a/compiler/tests/04_wordline_driver_test.py +++ b/compiler/tests/04_wordline_driver_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/05_bitcell_array_1rw_1r_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py index 6216475d..3ae9a7d7 100755 --- a/compiler/tests/05_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 916a4356..738a038e 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index c6831b90..41eb7b0b 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index ddefb588..8a05dcec 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_column_decoder_16row_test.py b/compiler/tests/06_column_decoder_16row_test.py index 2823b647..d34d6879 100755 --- a/compiler/tests/06_column_decoder_16row_test.py +++ b/compiler/tests/06_column_decoder_16row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py index 3c4ee7ee..26aeb899 100755 --- a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_132row_test.py b/compiler/tests/06_hierarchical_decoder_132row_test.py index 3681fcbf..d1655a25 100755 --- a/compiler/tests/06_hierarchical_decoder_132row_test.py +++ b/compiler/tests/06_hierarchical_decoder_132row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py index ea50b36c..aad79dd4 100755 --- a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_16row_test.py b/compiler/tests/06_hierarchical_decoder_16row_test.py index b3dd35aa..fc379cc4 100755 --- a/compiler/tests/06_hierarchical_decoder_16row_test.py +++ b/compiler/tests/06_hierarchical_decoder_16row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py index 549ce54f..d81f6774 100755 --- a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_17row_test.py b/compiler/tests/06_hierarchical_decoder_17row_test.py index f4407baa..ff7d1662 100755 --- a/compiler/tests/06_hierarchical_decoder_17row_test.py +++ b/compiler/tests/06_hierarchical_decoder_17row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py index 6c2f6bd6..7ec03133 100755 --- a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_32row_test.py b/compiler/tests/06_hierarchical_decoder_32row_test.py index 26bcffad..895b63dc 100755 --- a/compiler/tests/06_hierarchical_decoder_32row_test.py +++ b/compiler/tests/06_hierarchical_decoder_32row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py index 201fc399..c0058da4 100755 --- a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_4096row_test.py b/compiler/tests/06_hierarchical_decoder_4096row_test.py index 50e9bcaa..14e3f113 100755 --- a/compiler/tests/06_hierarchical_decoder_4096row_test.py +++ b/compiler/tests/06_hierarchical_decoder_4096row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py index f53f4838..5982e930 100755 --- a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_512row_test.py b/compiler/tests/06_hierarchical_decoder_512row_test.py index 5bcfff11..6ad92d86 100755 --- a/compiler/tests/06_hierarchical_decoder_512row_test.py +++ b/compiler/tests/06_hierarchical_decoder_512row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py index af9fb4f4..6dd3b4de 100755 --- a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_64row_test.py b/compiler/tests/06_hierarchical_decoder_64row_test.py index 0ef767e9..37b97732 100755 --- a/compiler/tests/06_hierarchical_decoder_64row_test.py +++ b/compiler/tests/06_hierarchical_decoder_64row_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index 002317b4..2548e498 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py index 8a33451f..0cff264a 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py index f634225e..bb9523a9 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index ff982cc0..d8680f53 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py index 3c67fb68..d6580991 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py index 9420fd72..1ddc91df 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index eb139537..3ff4a252 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/06_hierarchical_predecode4x16_test.py b/compiler/tests/06_hierarchical_predecode4x16_test.py index 8ebbb58a..ff855601 100755 --- a/compiler/tests/06_hierarchical_predecode4x16_test.py +++ b/compiler/tests/06_hierarchical_predecode4x16_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py index 9ef7da3e..36d086a8 100755 --- a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_16mux_test.py b/compiler/tests/07_column_mux_array_16mux_test.py index 67a7f9a4..51634eae 100755 --- a/compiler/tests/07_column_mux_array_16mux_test.py +++ b/compiler/tests/07_column_mux_array_16mux_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py index 10012e81..f217720e 100755 --- a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_2mux_test.py b/compiler/tests/07_column_mux_array_2mux_test.py index e8303c45..ba5145a4 100755 --- a/compiler/tests/07_column_mux_array_2mux_test.py +++ b/compiler/tests/07_column_mux_array_2mux_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py index 96123cae..8f4fc364 100755 --- a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_4mux_test.py b/compiler/tests/07_column_mux_array_4mux_test.py index 655bda54..0d637ef6 100755 --- a/compiler/tests/07_column_mux_array_4mux_test.py +++ b/compiler/tests/07_column_mux_array_4mux_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py index 9f85e3ac..7d2f248e 100755 --- a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_8mux_test.py b/compiler/tests/07_column_mux_array_8mux_test.py index eab6560a..468d6507 100755 --- a/compiler/tests/07_column_mux_array_8mux_test.py +++ b/compiler/tests/07_column_mux_array_8mux_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/07_column_mux_array_pbitcell_test.py b/compiler/tests/07_column_mux_array_pbitcell_test.py index 9e7365c0..bceba919 100755 --- a/compiler/tests/07_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_column_mux_array_pbitcell_test.py @@ -8,7 +8,7 @@ # from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index 71cd9673..1cb4d12c 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 48bdc17b..39d87476 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/08_wordline_buffer_array_test.py b/compiler/tests/08_wordline_buffer_array_test.py index 3152810d..6ae422c4 100755 --- a/compiler/tests/08_wordline_buffer_array_test.py +++ b/compiler/tests/08_wordline_buffer_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py index b1daff3d..cbfa1825 100755 --- a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py +++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/08_wordline_driver_array_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py index 0e6cf594..f3398346 100755 --- a/compiler/tests/08_wordline_driver_array_pbitcell_test.py +++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/08_wordline_driver_array_test.py b/compiler/tests/08_wordline_driver_array_test.py index 9436caf0..ea982005 100755 --- a/compiler/tests/08_wordline_driver_array_test.py +++ b/compiler/tests/08_wordline_driver_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py index 48d3f744..8273a0ad 100755 --- a/compiler/tests/09_sense_amp_array_1rw_1r_test.py +++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/09_sense_amp_array_pbitcell_test.py b/compiler/tests/09_sense_amp_array_pbitcell_test.py index d65d8649..4dfd966d 100755 --- a/compiler/tests/09_sense_amp_array_pbitcell_test.py +++ b/compiler/tests/09_sense_amp_array_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys,os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py index 8af08d77..57429d2b 100755 --- a/compiler/tests/09_sense_amp_array_spare_cols_test.py +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index d0f38166..aa21f181 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py index 233d5c34..534d5904 100755 --- a/compiler/tests/10_write_driver_array_1rw_1r_test.py +++ b/compiler/tests/10_write_driver_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py index e3b2ba2a..cd5601ce 100755 --- a/compiler/tests/10_write_driver_array_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_pbitcell_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py index 3ee6e485..bacfbdd9 100755 --- a/compiler/tests/10_write_driver_array_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 994e210a..fc17301e 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py index b2b29217..02c76300 100755 --- a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py index 266fc73a..e609ba43 100755 --- a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index 843d1dc5..7c1fd7bc 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py index c59c4acd..806381b5 100755 --- a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py +++ b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py index c389c879..fe43d0f2 100755 --- a/compiler/tests/10_write_mask_and_array_pbitcell_test.py +++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 8cc9b685..8a667145 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -10,7 +10,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index d5ee0607..7d4779eb 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index 3e1d5eb3..e46a5f91 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index 47724f89..354e5188 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index af1229a3..b07dde74 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py index 8dad9f9b..0f905d75 100755 --- a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py index 3137802b..a07318f0 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py index 7f7ee74c..920a3d3e 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 33ba6b8e..fc938bfb 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py index 82b6437a..10ee5983 100755 --- a/compiler/tests/14_replica_column_1rw_1r_test.py +++ b/compiler/tests/14_replica_column_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index c8d50a53..73825e39 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py index b13bc56a..d72289a7 100755 --- a/compiler/tests/14_replica_pbitcell_array_test.py +++ b/compiler/tests/14_replica_pbitcell_array_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py index 9dab6ddd..d7701539 100755 --- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from sram_factory import factory import debug diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_test.py index 0f68227e..7f4b8154 100755 --- a/compiler/tests/15_global_bitcell_array_test.py +++ b/compiler/tests/15_global_bitcell_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from sram_factory import factory import debug diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index ae86f949..0826586c 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from sram_factory import factory import debug diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py index ae6a4dc0..30c9c8e9 100755 --- a/compiler/tests/15_local_bitcell_array_test.py +++ b/compiler/tests/15_local_bitcell_array_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from sram_factory import factory import debug diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index c90b55de..ae6ce538 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -13,7 +13,7 @@ Run a regression test on a control_logic import unittest from testutils import header,openram_test import sys, os -sys.path.append(os.path.join(sys.path[0],"..")) + import globals from globals import OPTS from sram_factory import factory @@ -24,8 +24,6 @@ class control_logic_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import control_logic - import tech # check control logic for multi-port OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/16_control_logic_r_test.py b/compiler/tests/16_control_logic_r_test.py index 74d95189..67fa2635 100755 --- a/compiler/tests/16_control_logic_r_test.py +++ b/compiler/tests/16_control_logic_r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/16_control_logic_rw_test.py b/compiler/tests/16_control_logic_rw_test.py index a6b375e4..dd83f623 100755 --- a/compiler/tests/16_control_logic_rw_test.py +++ b/compiler/tests/16_control_logic_rw_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/16_control_logic_w_test.py b/compiler/tests/16_control_logic_w_test.py index bbdd0c09..4a828fdf 100755 --- a/compiler/tests/16_control_logic_w_test.py +++ b/compiler/tests/16_control_logic_w_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/18_port_address_16rows_1rw_1r_test.py b/compiler/tests/18_port_address_16rows_1rw_1r_test.py index ff39eeed..ffca57d3 100755 --- a/compiler/tests/18_port_address_16rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_16rows_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/18_port_address_16rows_test.py b/compiler/tests/18_port_address_16rows_test.py index a60508de..36093297 100755 --- a/compiler/tests/18_port_address_16rows_test.py +++ b/compiler/tests/18_port_address_16rows_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/18_port_address_256rows_1rw_1r_test.py b/compiler/tests/18_port_address_256rows_1rw_1r_test.py index e9c11bd7..8fef71fc 100755 --- a/compiler/tests/18_port_address_256rows_1rw_1r_test.py +++ b/compiler/tests/18_port_address_256rows_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/18_port_address_512rows_test.py b/compiler/tests/18_port_address_512rows_test.py index 120ec9be..03f8c455 100755 --- a/compiler/tests/18_port_address_512rows_test.py +++ b/compiler/tests/18_port_address_512rows_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py index 83a453d0..15ff8eee 100755 --- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py index de0f2394..3415711b 100755 --- a/compiler/tests/18_port_data_16mux_test.py +++ b/compiler/tests/18_port_data_16mux_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py index 70e5e7df..d907b50c 100755 --- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py index f9b8916c..4b72d046 100755 --- a/compiler/tests/18_port_data_2mux_test.py +++ b/compiler/tests/18_port_data_2mux_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py index ddca3075..c5d163cf 100755 --- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py index 82cbe5d1..84136361 100755 --- a/compiler/tests/18_port_data_4mux_test.py +++ b/compiler/tests/18_port_data_4mux_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py index cc67c810..17c98ace 100755 --- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py index ec669f02..781954cc 100755 --- a/compiler/tests/18_port_data_8mux_test.py +++ b/compiler/tests/18_port_data_8mux_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py index 67a6b6eb..1c1197ee 100755 --- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py index 34298d8b..7d775cd5 100755 --- a/compiler/tests/18_port_data_nomux_test.py +++ b/compiler/tests/18_port_data_nomux_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 392aef1a..f52e33d4 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=8, num_words=16, diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index 5d72cffc..5f58f670 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -7,7 +7,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -19,7 +19,7 @@ class port_data_wmask_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index 4f08400b..406b6822 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -8,7 +8,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -20,7 +20,7 @@ class port_data_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_bank_select_pbitcell_test.py b/compiler/tests/19_bank_select_pbitcell_test.py deleted file mode 100755 index 2f427a35..00000000 --- a/compiler/tests/19_bank_select_pbitcell_test.py +++ /dev/null @@ -1,48 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2021 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import unittest -from testutils import * -import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) -import globals -from globals import OPTS -from sram_factory import factory -import debug - -class bank_select_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - - OPTS.bitcell = "pbitcell" - debug.info(1, "No column mux, rw control logic") - a = factory.create(module_type="bank_select", port="rw") - self.local_check(a) - - OPTS.num_rw_ports = 0 - OPTS.num_w_ports = 1 - OPTS.num_r_ports = 1 - - debug.info(1, "No column mux, w control logic") - a = factory.create(module_type="bank_select", port="w") - self.local_check(a) - - debug.info(1, "No column mux, r control logic") - a = factory.create(module_type="bank_select", port="r") - self.local_check(a) - - globals.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py deleted file mode 100755 index e3c7ece8..00000000 --- a/compiler/tests/19_bank_select_test.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env python3 -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2021 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import unittest -from testutils import * -import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) -import globals -from globals import OPTS -from sram_factory import factory -import debug - -class bank_select_test(openram_test): - - def runTest(self): - config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) - - debug.info(1, "No column mux, rw control logic") - a = factory.create(module_type="bank_select", port="rw") - self.local_check(a) - - globals.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 46b75697..e73a97fc 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class multi_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 099a8214..be2ba0c0 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class multi_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent) diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 09be0b3f..8aec720c 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psingle_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py index 6133ccad..adc5d33e 100755 --- a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_16mux_test.py b/compiler/tests/19_single_bank_16mux_test.py index 010703a9..8dd02db3 100755 --- a/compiler/tests/19_single_bank_16mux_test.py +++ b/compiler/tests/19_single_bank_16mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 6b6fe65c..31b8349b 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py index 15664c81..dbed3cc6 100755 --- a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_2mux_test.py b/compiler/tests/19_single_bank_2mux_test.py index d29de4e6..f5efc231 100755 --- a/compiler/tests/19_single_bank_2mux_test.py +++ b/compiler/tests/19_single_bank_2mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py index 9518373c..13387ac9 100755 --- a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_4mux_test.py b/compiler/tests/19_single_bank_4mux_test.py index 77459ff9..7a58b401 100755 --- a/compiler/tests/19_single_bank_4mux_test.py +++ b/compiler/tests/19_single_bank_4mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py index 11b74350..f03aadc6 100755 --- a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_8mux_test.py b/compiler/tests/19_single_bank_8mux_test.py index 1317fd61..56a3c549 100755 --- a/compiler/tests/19_single_bank_8mux_test.py +++ b/compiler/tests/19_single_bank_8mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_single_bank_global_bitline_test.py b/compiler/tests/19_single_bank_global_bitline_test.py index a99534c6..ead8decb 100755 --- a/compiler/tests/19_single_bank_global_bitline_test.py +++ b/compiler/tests/19_single_bank_global_bitline_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py index f165f991..afb1129b 100755 --- a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_nomux_test.py b/compiler/tests/19_single_bank_nomux_test.py index 1df7103d..6ae084ec 100755 --- a/compiler/tests/19_single_bank_nomux_test.py +++ b/compiler/tests/19_single_bank_nomux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index dd03b18e..97bcf5af 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -20,7 +20,7 @@ class single_bank_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py index 9fae4bb6..77f7ba2e 100755 --- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class single_bank_wmask_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 9e17f105..08fe19f4 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -20,7 +20,7 @@ class single_bank_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=8, diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 05927d26..e1970b2f 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 4a17bd05..a666f820 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 683b786b..51be2cab 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 0 diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 758d6b1c..133c81d1 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psram_1bank_2mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 345758ab..0995e49f 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py index 072a3f8d..93736a53 100755 --- a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_16mux_test.py b/compiler/tests/20_sram_1bank_16mux_test.py index 61f469e4..6461c5a6 100755 --- a/compiler/tests/20_sram_1bank_16mux_test.py +++ b/compiler/tests/20_sram_1bank_16mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_8mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py index 82409479..08922ede 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index af97d25a..b5d9d776 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py index b19cacc6..abbb2347 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 890ad24a..5eabef8b 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py index ec207564..fc4a32e8 100755 --- a/compiler/tests/20_sram_1bank_2mux_global_test.py +++ b/compiler/tests/20_sram_1bank_2mux_global_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_global_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.local_array_size = 8 if OPTS.tech_name == "sky130": diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 045eccec..85041348 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py index 0472793c..d24fa62f 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 65c0f399..84830d5c 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index 4a52c385..4df1bcca 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -22,7 +22,7 @@ class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py index 8bcc0415..2e59670f 100755 --- a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 6f87fe44..0fdf883a 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_4mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 33ef158f..bc1f824d 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index dc4ad5ec..a670744a 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_8mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index 323678f7..561074a1 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 8b0a1b58..e8e18b7a 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index d2b5da52..99131037 100755 --- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 7a13b28b..59e309df 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory @@ -21,7 +20,7 @@ class sram_1bank_nomux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py index f115a9b0..a7326df3 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -22,7 +22,7 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index 8c012a60..5eb10212 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -21,7 +21,7 @@ class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py index db2b5297..5010a3de 100755 --- a/compiler/tests/20_sram_1bank_ring_test.py +++ b/compiler/tests/20_sram_1bank_ring_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -22,7 +22,7 @@ class sram_1bank_nomux_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) OPTS.supply_pin_type = "ring" - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index da672801..e2d144bf 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -22,7 +22,7 @@ class sram_2bank_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=16, num_words=32, num_banks=2) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 987fffa8..a5677a13 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -30,7 +30,7 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 76f47d1a..0ebcb167 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 71b002e1..ab6f3888 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,8 +31,8 @@ class model_delay_test(openram_test): reload(characterizer) from characterizer import delay from characterizer import elmore - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index f5bcc658..3935ac3d 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -29,7 +29,7 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=1, num_words=16, num_banks=1, diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py index f826880c..94ed2aba 100755 --- a/compiler/tests/21_ngspice_delay_global_test.py +++ b/compiler/tests/21_ngspice_delay_global_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram_config import sram_config + from modules import sram_config OPTS.local_array_size = 2 if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index e13eada8..d5b952ac 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -29,7 +29,7 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 9bda2c2c..70adfaaa 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS diff --git a/compiler/tests/21_regression_delay_test.py b/compiler/tests/21_regression_delay_test.py index c79f0218..dbebba0d 100755 --- a/compiler/tests/21_regression_delay_test.py +++ b/compiler/tests/21_regression_delay_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,8 +31,8 @@ class regression_model_test(openram_test): reload(characterizer) from characterizer import linear_regression from characterizer import neural_network - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py index 6592b50e..705f432e 100755 --- a/compiler/tests/21_xyce_delay_test.py +++ b/compiler/tests/21_xyce_delay_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -30,7 +30,7 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py index 3aabce06..c2962c48 100755 --- a/compiler/tests/21_xyce_setuphold_test.py +++ b/compiler/tests/21_xyce_setuphold_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index f5f4cd8f..9d6d038e 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -38,7 +38,7 @@ class psram_1bank_2mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index f422728b..30943de1 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -39,7 +39,7 @@ class psram_1bank_4mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=2, num_words=256, num_banks=1) diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index f0247808..dd79e6b8 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -39,7 +39,7 @@ class psram_1bank_8mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=256, num_banks=1) diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 203fd0ac..e81cc87d 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -38,7 +38,7 @@ class psram_1bank_nomux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=2, num_words=32, num_banks=1) diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index dedbba0c..c7ac0d05 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_1bank_2mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py index 664815e7..dc4b1730 100755 --- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_1bank_2mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config OPTS.local_array_size = 8 if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py index 0466af79..20570a6c 100755 --- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index c08a4fef..7b397209 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_1bank_4mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index 6e6190e4..fcc38091 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -34,7 +34,7 @@ class sram_1bank_8mux_func_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py index c0518957..76116485 100755 --- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -35,7 +35,7 @@ class psram_1bank_nomux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index c0e4e19a..5617b3fe 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_1bank_nomux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py index 0116f444..5b3e0908 100755 --- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py index d2b62470..09b77170 100755 --- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py +++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -35,7 +35,7 @@ class sram_wmask_1w_1r_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index de10d9f6..570b515e 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -31,7 +31,7 @@ class sram_wmask_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 num_spare_cols = 1 diff --git a/compiler/tests/23_lib_sram_linear_regression_test.py b/compiler/tests/23_lib_sram_linear_regression_test.py index 620b8f0e..642c3b51 100755 --- a/compiler/tests/23_lib_sram_linear_regression_test.py +++ b/compiler/tests/23_lib_sram_linear_regression_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -32,8 +32,8 @@ class lib_sram_linear_regression_test(openram_test): num_spare_cols = 0 from characterizer import lib - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 1de09c2b..7a46aec5 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -31,8 +31,8 @@ class lib_model_corners_lib_test(openram_test): num_spare_cols = 0 from characterizer import lib - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index e421235e..ec918b00 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -31,8 +31,8 @@ class lib_sram_model_test(openram_test): num_spare_cols = 0 from characterizer import lib - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index ae9093f5..b509a1b9 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -39,8 +39,8 @@ class lib_sram_prune_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index cf9cf801..34397ada 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os,re -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -37,8 +37,8 @@ class lib_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1, diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 43638003..675daed8 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -23,8 +23,8 @@ class lef_test(openram_test): globals.init_openram(config_file) OPTS.route_supplies=False OPTS.check_lvsdrc=False - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1) diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 63658d04..be2528b6 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug @@ -23,8 +23,8 @@ class verilog_test(openram_test): OPTS.route_supplies=False OPTS.check_lvsdrc=False OPTS.netlist_only=True - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=1) diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index 3246913b..7dbd56a6 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -11,7 +11,7 @@ with HSPICE. import unittest from testutils import header, openram_test import sys, os -sys.path.append(os.path.join(sys.path[0],"..")) + import globals from globals import OPTS import debug diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index d53f2d2c..c2582237 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -11,7 +11,7 @@ with Ngspice. import unittest from testutils import header,openram_test import sys, os -sys.path.append(os.path.join(sys.path[0],"..")) + import globals from globals import OPTS import debug diff --git a/compiler/tests/26_sram_pex_test.py b/compiler/tests/26_sram_pex_test.py index 90dd46ee..c8b101cb 100755 --- a/compiler/tests/26_sram_pex_test.py +++ b/compiler/tests/26_sram_pex_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -30,7 +30,7 @@ class sram_pex_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=4, num_words=32, num_banks=1) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index c67b8249..e0233ead 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os, re, shutil -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 87b280dc..489ea26c 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os, re, shutil -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS import debug diff --git a/compiler/tests/50_riscv_1k_1rw1r_func_test.py b/compiler/tests/50_riscv_1k_1rw1r_func_test.py index 6cd494aa..2b770111 100755 --- a/compiler/tests/50_riscv_1k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_1k_1rw1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=256, diff --git a/compiler/tests/50_riscv_1k_1rw_func_test.py b/compiler/tests/50_riscv_1k_1rw_func_test.py index a99fba03..9623f4af 100755 --- a/compiler/tests/50_riscv_1k_1rw_func_test.py +++ b/compiler/tests/50_riscv_1k_1rw_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=256, diff --git a/compiler/tests/50_riscv_1rw1r_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py index 19609159..4b864193 100755 --- a/compiler/tests/50_riscv_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_1rw1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -36,7 +36,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=32, diff --git a/compiler/tests/50_riscv_1rw1r_phys_test.py b/compiler/tests/50_riscv_1rw1r_phys_test.py index 40ae942f..47774828 100755 --- a/compiler/tests/50_riscv_1rw1r_phys_test.py +++ b/compiler/tests/50_riscv_1rw1r_phys_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -22,7 +22,7 @@ class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py index 0e7e79d7..ee157a44 100755 --- a/compiler/tests/50_riscv_1rw_func_test.py +++ b/compiler/tests/50_riscv_1rw_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -44,7 +44,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=64, diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py index 4cf2def5..c4e574c1 100755 --- a/compiler/tests/50_riscv_1rw_phys_test.py +++ b/compiler/tests/50_riscv_1rw_phys_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -22,7 +22,7 @@ class riscv_phys_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - from sram_config import sram_config + from modules import sram_config if OPTS.tech_name == "sky130": num_spare_rows = 1 diff --git a/compiler/tests/50_riscv_2k_1rw1r_func_test.py b/compiler/tests/50_riscv_2k_1rw1r_func_test.py index 2fa1ec47..ffa7ca03 100755 --- a/compiler/tests/50_riscv_2k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_2k_1rw1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=512, diff --git a/compiler/tests/50_riscv_2k_1rw_func_test.py b/compiler/tests/50_riscv_2k_1rw_func_test.py index 24ec2e3a..a48a03c0 100755 --- a/compiler/tests/50_riscv_2k_1rw_func_test.py +++ b/compiler/tests/50_riscv_2k_1rw_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=512, diff --git a/compiler/tests/50_riscv_4k_1rw1r_func_test.py b/compiler/tests/50_riscv_4k_1rw1r_func_test.py index 6b4f336e..431b5390 100755 --- a/compiler/tests/50_riscv_4k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_4k_1rw1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=1024, diff --git a/compiler/tests/50_riscv_4k_1rw_func_test.py b/compiler/tests/50_riscv_4k_1rw_func_test.py index 9f2dc2f6..45254ac4 100755 --- a/compiler/tests/50_riscv_4k_1rw_func_test.py +++ b/compiler/tests/50_riscv_4k_1rw_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=1024, diff --git a/compiler/tests/50_riscv_512b_1rw1r_func_test.py b/compiler/tests/50_riscv_512b_1rw1r_func_test.py index 17b3f518..26682139 100755 --- a/compiler/tests/50_riscv_512b_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_512b_1rw1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=128, diff --git a/compiler/tests/50_riscv_512b_1rw_func_test.py b/compiler/tests/50_riscv_512b_1rw_func_test.py index 4cceefd8..0af228a9 100755 --- a/compiler/tests/50_riscv_512b_1rw_func_test.py +++ b/compiler/tests/50_riscv_512b_1rw_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=128, diff --git a/compiler/tests/50_riscv_8k_1rw1r_func_test.py b/compiler/tests/50_riscv_8k_1rw1r_func_test.py index 0783823c..f2861bad 100755 --- a/compiler/tests/50_riscv_8k_1rw1r_func_test.py +++ b/compiler/tests/50_riscv_8k_1rw1r_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=2048, diff --git a/compiler/tests/50_riscv_8k_1rw_func_test.py b/compiler/tests/50_riscv_8k_1rw_func_test.py index 7b948aad..22db186e 100755 --- a/compiler/tests/50_riscv_8k_1rw_func_test.py +++ b/compiler/tests/50_riscv_8k_1rw_func_test.py @@ -9,7 +9,7 @@ import unittest from testutils import * import sys, os -sys.path.append(os.getenv("OPENRAM_HOME")) + import globals from globals import OPTS from sram_factory import factory @@ -37,7 +37,7 @@ class riscv_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram_config import sram_config + from modules import sram_config c = sram_config(word_size=32, write_size=8, num_words=2048, diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 67c08d2e..bd4a7aa2 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -7,7 +7,6 @@ # import unittest import sys, os, glob -sys.path.append(os.getenv("OPENRAM_HOME")) from globals import OPTS import debug import pdb @@ -140,8 +139,8 @@ class openram_test(unittest.TestCase): Reset everything after each test. """ # Reset the static duplicate name checker for unit tests. - import hierarchy_design - hierarchy_design.hierarchy_design.name_map=[] + from base import hierarchy_design + hierarchy_design.name_map=[] def check_golden_data(self, data, golden_data, error_tolerance=1e-2): """ diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 53b2f167..0de27ba9 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -18,12 +18,10 @@ Calibre means pointing the code to the proper DRC and LVS rule files. import os -import shutil import re import debug -import utils from globals import OPTS -from run_script import run_script +from .run_script import run_script # Keep track of statistics num_drc_runs = 0 diff --git a/compiler/verify/klayout.py b/compiler/verify/klayout.py index ca19e79b..73cec474 100644 --- a/compiler/verify/klayout.py +++ b/compiler/verify/klayout.py @@ -16,7 +16,7 @@ import re import shutil import debug from globals import OPTS -from run_script import * +from .run_script import * # Keep track of statistics num_drc_runs = 0 diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 2b5727ed..e3cd8515 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -25,7 +25,7 @@ import re import shutil import debug from globals import OPTS -from run_script import * +from .run_script import * # Keep track of statistics num_drc_runs = 0 @@ -270,7 +270,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out setup_file_object = open(output_path + "/setup.tcl", 'a') setup_file_object.write("# Increase the column sizes for ease of reading long names\n") - setup_file_object.write("::netgen::format 80\n") + setup_file_object.write("::netgen::format 120\n") else: setup_file = 'nosetup' diff --git a/openram.mk b/openram.mk index b0e57268..be987aaf 100644 --- a/openram.mk +++ b/openram.mk @@ -27,6 +27,7 @@ export DOCKER_CMD= docker run \ -e OPENRAM_HOME=/openram/compiler \ -e OPENRAM_TECH=/openram/technology \ -e OPENRAM_TMP=$(OPENRAM_DIR)/results/$*/tmp \ + -e PYTHONPATH=/openram/compiler \ -v /etc/passwd:/etc/passwd:ro -v /etc/group:/etc/group:ro \ --user $(UID):$(GID) \ vlsida/openram-ubuntu:latest @@ -41,6 +42,7 @@ mount: -e PDKPATH=/pdk/sky130A \ -e OPENRAM_HOME=/openram/compiler \ -e OPENRAM_TECH=/openram/technology \ + -e PYTHONPATH=/openram/compiler \ -v /etc/passwd:/etc/passwd:ro -v /etc/group:/etc/group:ro \ --user $(UID):$(GID) \ vlsida/openram-ubuntu:latest diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 7c1ac84b..76522ff3 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -6,10 +6,11 @@ # All rights reserved. # import os -from design_rules import * -from module_type import * -from custom_cell_properties import cell_properties -from custom_layer_properties import layer_properties +import drc as d +#from drc.design_rules import design_rules +#from drc.module_type import module_type +#from drc.custom_cell_properties import cell_properties +#from drc.custom_layer_properties import layer_properties """ File containing the process technology parameters for FreePDK 45nm. @@ -24,18 +25,18 @@ File containing the process technology parameters for FreePDK 45nm. # Using tech_modules['cellname'] you can override each class by providing a custom # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_freepdk45' -tech_modules = module_type() +tech_modules = d.module_type() ################################################### # Custom cell properties ################################################### -cell_properties = cell_properties() +cell_properties = d.cell_properties() ################################################### # Custom cell properties ################################################### -layer_properties = layer_properties() +layer_properties = d.layer_properties() ################################################### # GDS file info @@ -185,7 +186,7 @@ parameter["6T_access_size"] = 0.135 drclvs_home=os.environ.get("DRCLVS_HOME") -drc = design_rules("freepdk45") +drc = d.design_rules("freepdk45") #grid size drc["grid"] = 0.0025 @@ -347,7 +348,7 @@ drc.add_layer("via2", # Minimum spacing of m3 wider than 1.5 & longer than 4.0=1.5 drc.add_layer("m3", width=0.07, - spacing=drc_lut({(0.00, 0.0): 0.07, + spacing=d.drc_lut({(0.00, 0.0): 0.07, (0.09, 0.3): 0.09, (0.27, 0.9): 0.27, (0.50, 1.8): 0.5, @@ -379,7 +380,7 @@ drc.add_layer("via3", # Minimum spacing of m4 wider than 1.5 & longer than 4.0=1.5 drc.add_layer("m4", width=0.14, - spacing=drc_lut({(0.00, 0.0): 0.14, + spacing=d.drc_lut({(0.00, 0.0): 0.14, (0.27, 0.9): 0.27, (0.50, 1.8): 0.5, (0.90, 2.7): 0.9, diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 525736a8..e940ce29 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -6,10 +6,11 @@ # All rights reserved. # import os -from design_rules import * -from module_type import * -from custom_cell_properties import cell_properties -from custom_layer_properties import layer_properties +import drc as d +#from drc.design_rules import design_rules +#from drc.module_type import module_type +#from drc.custom_cell_properties import cell_properties +#from drc.custom_layer_properties import layer_properties """ File containing the process technology parameters for SCMOS 4m, 0.35um @@ -24,19 +25,19 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # Using tech_modules['cellname'] you can override each class by providing a custom # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_scn4m' -tech_modules = module_type() +tech_modules = d.module_type() ################################################### # Custom cell properties ################################################### -cell_properties = cell_properties() +cell_properties = d.cell_properties() cell_properties.bitcell_1port.gnd_layer = "m2" cell_properties.bitcell_1port.gnd_dir = "V" ################################################### # Custom cell properties ################################################### -layer_properties = layer_properties() +layer_properties = d.layer_properties() ################################################### # GDS file info @@ -160,7 +161,7 @@ parameter["6T_access_size"] = 4*_lambda_ drclvs_home=os.environ.get("DRCLVS_HOME") -drc = design_rules("scn4me_sub") +drc = d.design_rules("scn4me_sub") #grid size is 1/2 a lambda drc["grid"]=0.5*_lambda_ diff --git a/technology/sky130/custom/__init__.py b/technology/sky130/custom/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/technology/sky130/modules/sky130_bitcell.py b/technology/sky130/custom/sky130_bitcell.py similarity index 94% rename from technology/sky130/modules/sky130_bitcell.py rename to technology/sky130/custom/sky130_bitcell.py index 90371a29..908ff45d 100644 --- a/technology/sky130/modules/sky130_bitcell.py +++ b/technology/sky130/custom/sky130_bitcell.py @@ -7,10 +7,10 @@ import debug from tech import cell_properties as props -import bitcell_base +from modules import bitcell_base -class sky130_bitcell(bitcell_base.bitcell_base): +class sky130_bitcell(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so diff --git a/technology/sky130/modules/sky130_bitcell_array.py b/technology/sky130/custom/sky130_bitcell_array.py similarity index 97% rename from technology/sky130/modules/sky130_bitcell_array.py rename to technology/sky130/custom/sky130_bitcell_array.py index 9910cbd5..2c7f5cd5 100644 --- a/technology/sky130/modules/sky130_bitcell_array.py +++ b/technology/sky130/custom/sky130_bitcell_array.py @@ -6,8 +6,8 @@ # import debug -from bitcell_array import bitcell_array -from sky130_bitcell_base_array import sky130_bitcell_base_array +from modules import bitcell_array +from .sky130_bitcell_base_array import sky130_bitcell_base_array from globals import OPTS from sram_factory import factory diff --git a/technology/sky130/modules/sky130_bitcell_base_array.py b/technology/sky130/custom/sky130_bitcell_base_array.py similarity index 99% rename from technology/sky130/modules/sky130_bitcell_base_array.py rename to technology/sky130/custom/sky130_bitcell_base_array.py index adaf1304..1604fa02 100644 --- a/technology/sky130/modules/sky130_bitcell_base_array.py +++ b/technology/sky130/custom/sky130_bitcell_base_array.py @@ -6,9 +6,9 @@ # import debug -import geometry +from base import geometry from sram_factory import factory -from bitcell_base_array import bitcell_base_array +from modules import bitcell_base_array from globals import OPTS from tech import layer diff --git a/technology/sky130/modules/sky130_col_cap.py b/technology/sky130/custom/sky130_col_cap.py similarity index 96% rename from technology/sky130/modules/sky130_col_cap.py rename to technology/sky130/custom/sky130_col_cap.py index cd328754..eb2383e5 100644 --- a/technology/sky130/modules/sky130_col_cap.py +++ b/technology/sky130/custom/sky130_col_cap.py @@ -6,11 +6,11 @@ # import debug -import design +from base import design from tech import cell_properties as props -class sky130_col_cap(design.design): +class sky130_col_cap(design): def __init__(self, version, name=""): if version == "colend": diff --git a/technology/sky130/modules/sky130_col_cap_array.py b/technology/sky130/custom/sky130_col_cap_array.py similarity index 99% rename from technology/sky130/modules/sky130_col_cap_array.py rename to technology/sky130/custom/sky130_col_cap_array.py index 214a53a8..940296d3 100644 --- a/technology/sky130/modules/sky130_col_cap_array.py +++ b/technology/sky130/custom/sky130_col_cap_array.py @@ -6,9 +6,9 @@ # from sram_factory import factory -from sky130_bitcell_base_array import sky130_bitcell_base_array +from .sky130_bitcell_base_array import sky130_bitcell_base_array from globals import OPTS -import geometry +from base import geometry from tech import layer class sky130_col_cap_array(sky130_bitcell_base_array): diff --git a/technology/sky130/modules/sky130_corner.py b/technology/sky130/custom/sky130_corner.py similarity index 63% rename from technology/sky130/modules/sky130_corner.py rename to technology/sky130/custom/sky130_corner.py index 4c5594a2..858a0a4a 100644 --- a/technology/sky130/modules/sky130_corner.py +++ b/technology/sky130/custom/sky130_corner.py @@ -6,12 +6,12 @@ # import debug -import design -import utils +from base import design +from base import get_libcell_size from tech import layer, GDS -class sky130_corner(design.design): +class sky130_corner(design): def __init__(self, location, name=""): super().__init__(name) @@ -26,8 +26,8 @@ class sky130_corner(design.design): self.name = "sky130_fd_bd_sram__sram_sp_cornera" else: debug.error("Invalid sky130_corner location", -1) - design.design.__init__(self, name=self.name) - (self.width, self.height) = utils.get_libcell_size(self.name, - GDS["unit"], - layer["mem"]) - # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"]) + design.__init__(self, name=self.name) + (self.width, self.height) = get_libcell_size(self.name, + GDS["unit"], + layer["mem"]) + # pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"]) diff --git a/technology/sky130/modules/sky130_dummy_array.py b/technology/sky130/custom/sky130_dummy_array.py similarity index 98% rename from technology/sky130/modules/sky130_dummy_array.py rename to technology/sky130/custom/sky130_dummy_array.py index 246a7f86..bfdca620 100644 --- a/technology/sky130/modules/sky130_dummy_array.py +++ b/technology/sky130/custom/sky130_dummy_array.py @@ -5,10 +5,10 @@ # All rights reserved. # -from sky130_bitcell_base_array import sky130_bitcell_base_array +from .sky130_bitcell_base_array import sky130_bitcell_base_array from sram_factory import factory from globals import OPTS -import geometry +from base import geometry from tech import layer class sky130_dummy_array(sky130_bitcell_base_array): diff --git a/technology/sky130/modules/sky130_dummy_bitcell.py b/technology/sky130/custom/sky130_dummy_bitcell.py similarity index 91% rename from technology/sky130/modules/sky130_dummy_bitcell.py rename to technology/sky130/custom/sky130_dummy_bitcell.py index 044c2848..58ef8026 100644 --- a/technology/sky130/modules/sky130_dummy_bitcell.py +++ b/technology/sky130/custom/sky130_dummy_bitcell.py @@ -7,10 +7,10 @@ import debug from tech import cell_properties as props -import bitcell_base +from modules import bitcell_base -class sky130_dummy_bitcell(bitcell_base.bitcell_base): +class sky130_dummy_bitcell(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It is a hand-made cell, so diff --git a/technology/sky130/modules/sky130_internal.py b/technology/sky130/custom/sky130_internal.py similarity index 64% rename from technology/sky130/modules/sky130_internal.py rename to technology/sky130/custom/sky130_internal.py index b8c0616f..10637384 100644 --- a/technology/sky130/modules/sky130_internal.py +++ b/technology/sky130/custom/sky130_internal.py @@ -6,12 +6,12 @@ # import debug -import design -import utils +from base import design +from base import get_libcell_size from tech import layer, GDS -class sky130_internal(design.design): +class sky130_internal(design): def __init__(self, version, name=""): super().__init__(name) @@ -26,8 +26,8 @@ class sky130_internal(design.design): self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p" else: debug.error("Invalid version", -1) - design.design.__init__(self, name=self.name) - (self.width, self.height) = utils.get_libcell_size(self.name, - GDS["unit"], - layer["mem"]) - # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"]) + design.__init__(self, name=self.name) + (self.width, self.height) = get_libcell_size(self.name, + GDS["unit"], + layer["mem"]) + # pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"]) diff --git a/technology/sky130/modules/sky130_replica_bitcell.py b/technology/sky130/custom/sky130_replica_bitcell.py similarity index 90% rename from technology/sky130/modules/sky130_replica_bitcell.py rename to technology/sky130/custom/sky130_replica_bitcell.py index 8be40adc..2b30fb7a 100644 --- a/technology/sky130/modules/sky130_replica_bitcell.py +++ b/technology/sky130/custom/sky130_replica_bitcell.py @@ -6,13 +6,13 @@ # import debug -import bitcell_base +from modules import bitcell_base +from base import logical_effort from tech import parameter, drc from tech import cell_properties as props -import logical_effort -class sky130_replica_bitcell(bitcell_base.bitcell_base): +class sky130_replica_bitcell(bitcell_base): """ A single bit cell (6T, 8T, etc.) This module implements the single memory cell used in the design. It @@ -32,7 +32,7 @@ class sky130_replica_bitcell(bitcell_base.bitcell_base): size = 0.5 # This accounts for bitline being drained thought the access TX and internal node cin = 3 # Assumes always a minimum sizes inverter. Could be specified in the tech.py file. read_port_load = 0.5 # min size NMOS gate load - return logical_effort.logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) + return logical_effort('bitline', size, cin, load + read_port_load, parasitic_delay, False) def input_load(self): """Return the relative capacitance of the access transistor gates""" diff --git a/technology/sky130/modules/sky130_replica_bitcell_array.py b/technology/sky130/custom/sky130_replica_bitcell_array.py similarity index 99% rename from technology/sky130/modules/sky130_replica_bitcell_array.py rename to technology/sky130/custom/sky130_replica_bitcell_array.py index 09e00d4c..c7b3c609 100644 --- a/technology/sky130/modules/sky130_replica_bitcell_array.py +++ b/technology/sky130/custom/sky130_replica_bitcell_array.py @@ -6,10 +6,10 @@ # import debug -from replica_bitcell_array import replica_bitcell_array -from vector import vector -from sky130_bitcell_base_array import sky130_bitcell_base_array -from utils import round_to_grid +from modules import replica_bitcell_array +from base import vector +from .sky130_bitcell_base_array import sky130_bitcell_base_array +from base import round_to_grid from math import sqrt from tech import drc from tech import array_row_multiple diff --git a/technology/sky130/modules/sky130_replica_column.py b/technology/sky130/custom/sky130_replica_column.py similarity index 99% rename from technology/sky130/modules/sky130_replica_column.py rename to technology/sky130/custom/sky130_replica_column.py index f05f91b8..8997d4f2 100644 --- a/technology/sky130/modules/sky130_replica_column.py +++ b/technology/sky130/custom/sky130_replica_column.py @@ -6,10 +6,10 @@ # import debug -from sky130_bitcell_base_array import sky130_bitcell_base_array +from .sky130_bitcell_base_array import sky130_bitcell_base_array from sram_factory import factory from globals import OPTS -import geometry +from base import geometry from tech import layer diff --git a/technology/sky130/modules/sky130_row_cap.py b/technology/sky130/custom/sky130_row_cap.py similarity index 93% rename from technology/sky130/modules/sky130_row_cap.py rename to technology/sky130/custom/sky130_row_cap.py index bdd0aa95..1c81b8dd 100644 --- a/technology/sky130/modules/sky130_row_cap.py +++ b/technology/sky130/custom/sky130_row_cap.py @@ -6,11 +6,11 @@ # import debug -import design +from base import design from tech import cell_properties as props -class sky130_row_cap(design.design): +class sky130_row_cap(design): def __init__(self, version, name=""): diff --git a/technology/sky130/modules/sky130_row_cap_array.py b/technology/sky130/custom/sky130_row_cap_array.py similarity index 98% rename from technology/sky130/modules/sky130_row_cap_array.py rename to technology/sky130/custom/sky130_row_cap_array.py index e5721da2..45b63c77 100644 --- a/technology/sky130/modules/sky130_row_cap_array.py +++ b/technology/sky130/custom/sky130_row_cap_array.py @@ -6,7 +6,7 @@ # from sram_factory import factory -from sky130_bitcell_base_array import sky130_bitcell_base_array +from .sky130_bitcell_base_array import sky130_bitcell_base_array from globals import OPTS diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py index 9eec156b..8eea88f1 100644 --- a/technology/sky130/tech/tech.py +++ b/technology/sky130/tech/tech.py @@ -7,10 +7,7 @@ import os -from design_rules import * -from module_type import * -from custom_cell_properties import cell_properties, cell -from custom_layer_properties import layer_properties +import drc as d """ File containing the process technology parameters for Skywater 130nm. @@ -25,7 +22,7 @@ File containing the process technology parameters for Skywater 130nm. # Using tech_modules['cellname'] you can override each class by providing a custom # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules["contact"] = "contact_freepdk45" -tech_modules = module_type() +tech_modules = d.module_type() # These modules have been hand designed and provided in this repository. tech_modules["nand2_dec"] = "nand2_dec" @@ -68,7 +65,7 @@ tech_modules["and4_dec"] = "and4_dec" ################################################### # Custom cell properties ################################################### -cell_properties = cell_properties() +cell_properties = d.cell_properties() cell_properties.bitcell_power_pin_directions = ("H", "H") @@ -116,7 +113,7 @@ cell_properties.bitcell_2port.vdd_dir = "H" cell_properties.bitcell_2port.gnd_layer = "m2" cell_properties.bitcell_2port.gnd_dir = "H" -cell_properties.col_cap_1port_bitcell = cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'], +cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'], ['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT', 'BIAS', 'BIAS'], {'bl': 'bl', 'br': 'br', @@ -127,21 +124,21 @@ cell_properties.col_cap_1port_bitcell = cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb': 'vpb'}) cell_properties.col_cap_1port_bitcell.boundary_layer = "mem" -cell_properties.col_cap_1port_strap_power = cell(['vdd', 'vpb', 'vnb'], +cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'], ['POWER', 'BIAS', 'BIAS'], {'vnb': 'VNB', 'vpb': 'VPB', 'vdd': 'VPWR'}) cell_properties.col_cap_1port_strap_power.boundary_layer = "mem" -cell_properties.col_cap_1port_strap_ground = cell(['gnd', 'vpb', 'vnb'], +cell_properties.col_cap_1port_strap_ground = d.cell(['gnd', 'vpb', 'vnb'], ['GROUND', 'BIAS', 'BIAS'], {'vnb': 'VNB', 'vpb': 'VPB', 'gnd': 'VGND'}) cell_properties.col_cap_1port_strap_ground.boundary_layer = "mem" -cell_properties.row_cap_1port_cell = cell(['vdd', 'wl'], +cell_properties.row_cap_1port_cell = d.cell(['vdd', 'wl'], ['POWER', 'INPUT'], {'wl': 'WL', 'vdd': 'VPWR'}) @@ -235,10 +232,11 @@ cell_properties.names["write_driver"] = "sky130_fd_bd_sram__openram_write_driver array_row_multiple = 2 array_col_multiple = 2 + ################################################### # Custom layer properties ################################################### -layer_properties = layer_properties() +layer_properties = d.layer_properties() layer_properties.hierarchical_decoder.bus_layer = "m1" layer_properties.hierarchical_decoder.bus_directions = "nonpref" layer_properties.hierarchical_decoder.input_layer = "li" @@ -469,7 +467,7 @@ parameter["6T_inv_nmos_size"] = 0.205 parameter["6T_inv_pmos_size"] = 0.09 parameter["6T_access_size"] = 0.135 -drc = design_rules("sky130") +drc = d.design_rules("sky130") # grid size drc["grid"] = 0.005