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fix capped array after merge with dev

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samuelkcrow
2022-12-14 14:20:54 -08:00
parent f651b484c5
commit d8e0f4275d
1 changed files with 7 additions and 7 deletions
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compiler/modules/capped_bitcell_array.py
+7 -7
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@@ -4,14 +4,14 @@
# All rights reserved.
#
import debug
from base import vector
from base import contact
from openram import debug
from openram.base import vector
from openram.base import contact
from openram.sram_factory import factory
from openram.tech import drc, spice
from openram.tech import cell_properties as props
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
from tech import drc, spice
from tech import cell_properties as props
from globals import OPTS
from sram_factory import factory
class capped_bitcell_array(bitcell_base_array):