diff --git a/compiler/modules/capped_bitcell_array.py b/compiler/modules/capped_bitcell_array.py
index 1c9d2d51..1751fd71 100644
--- a/compiler/modules/capped_bitcell_array.py
+++ b/compiler/modules/capped_bitcell_array.py
@@ -4,14 +4,14 @@
 # All rights reserved.
 #
 
-import debug
-from base import vector
-from base import contact
+from openram import debug
+from openram.base import vector
+from openram.base import contact
+from openram.sram_factory import factory
+from openram.tech import drc, spice
+from openram.tech import cell_properties as props
+from openram import OPTS
 from .bitcell_base_array import bitcell_base_array
-from tech import drc, spice
-from tech import cell_properties as props
-from globals import OPTS
-from sram_factory import factory
 
 
 class capped_bitcell_array(bitcell_base_array):