crba passing again norbl/leftrbl

compiler/modules/pattern.py

@@ -193,7 +193,7 @@ class pattern():
         for row in range(self.row_max+1):
             x = 0
             for col in range(self.col_max+1):
-                inst = self.parent_design.all_inst[row, col]
+                inst = self.parent_design.all_inst[self.row_max - row, col]
                 self.place_inst(inst, (x, y))
                 x += inst.width
             y += inst.height

compiler/modules/replica_bitcell_array.py

@@ -325,14 +325,15 @@ class replica_bitcell_array(bitcell_base_array):
 
         # Replica wordlines (go by the row instead of replica column because we may have to add a pin
         # even though the column is in another local bitcell array)
-        for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
-            for (wl_name, pin_name) in zip(names, self.dummy_rows[0].get_wordline_names()):
-                pin = inst.get_pin(pin_name)
-                self.add_layout_pin(text=wl_name,
-                                    layer=pin.layer,
-                                    offset=pin.ll().scale(0, 1),
-                                    width=self.width,
-                                    height=pin.height())
+        if self.rbl != [0,0]:
+            for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
+                for (wl_name, pin_name) in zip(names, self.dummy_rows[0].get_wordline_names()):
+                    pin = inst.get_pin(pin_name)
+                    self.add_layout_pin(text=wl_name,
+                                        layer=pin.layer,
+                                        offset=pin.ll().scale(0, 1),
+                                        width=self.width,
+                                        height=pin.height())
 
         # Main array bl/br
         for pin_name in self.all_bitline_names:

compiler/modules/replica_column.py

@@ -100,14 +100,13 @@ class replica_column(bitcell_base_array):
                 else:
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True, mirror='MX')
             else:
-                if current_row %2 == 0:
+                if current_row % 2 == 0:
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
                 else:
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True, mirror='MX')
 
             current_row += 1
         if self.cell.mirror.y:
-            print(self.column_offset)
             for row in range(self.total_size):
                 if self.column_offset % 2 == 0:
                     if core_block[row][0].mirror=='MX':

compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py

@@ -26,7 +26,7 @@ class capped_replica_bitcell_array_norbl_1rw_test(openram_test):
         openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row")
-        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=8, rows=6, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()

compiler/tests/Makefile

@@ -1,3 +1,4 @@
+SHELL := /bin/bash
 TOP_DIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST)))../..)
 include $(TOP_DIR)/openram.mk