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array generation and bitline routing with array module

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This commit is contained in:
Jacob Walker
2023-03-30 11:30:50 -07:00
parent 4db5c3be26
commit d7ac26a053
2 changed files with 123 additions and 41 deletions
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compiler/tests/05_rom_array_test.py
+2 -2
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@@ -24,7 +24,7 @@ class rom_array_test(openram_test):
debug.info(2, "Testing 4x4 array for rom cell")
data = [[1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1]]
data = [[1, 1, 1, 1], [1, 1, 1, 1], [1, 0, 1, 1], [1, 1, 1, 0]]
a = factory.create(module_type="rom_base_array", cols=4, rows=4, bitmap=data)
self.local_check(a)
@@ -36,4 +36,4 @@ if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
unittest.main(testRunner=debugTestRunner())