fix column mux without rbl start_bit to 0

2023-07-05 13:17:46 -07:00 · 2023-07-05 13:17:46 -07:00 · d65ccfcc95
parent b4a9784835
commit d65ccfcc95
1 changed files with 1 additions and 1 deletions
--- a/compiler/modules/port_data.py
+++ b/compiler/modules/port_data.py
@ -543,7 +543,7 @@ class port_data(design):
        if self.col_addr_size==0:
            return

-        start_bit = 1 if self.port == 0 else 0
+        start_bit = 1 if self.port == 0 and self.has_rbl else 0

        self.connect_bitlines(inst1=self.column_mux_array_inst,
                              inst2=self.precharge_array_inst,