From d65ccfcc95b9025d23d0a75ef05dc61e443a0f08 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 5 Jul 2023 13:17:46 -0700 Subject: [PATCH] fix column mux without rbl start_bit to 0 --- compiler/modules/port_data.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index cefdb871..aef91b7c 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -543,7 +543,7 @@ class port_data(design): if self.col_addr_size==0: return - start_bit = 1 if self.port == 0 else 0 + start_bit = 1 if self.port == 0 and self.has_rbl else 0 self.connect_bitlines(inst1=self.column_mux_array_inst, inst2=self.precharge_array_inst,