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Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

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This commit is contained in:
Hunter Nichols
2019-05-07 00:52:27 -07:00
parent 5bfc42fdbb
commit d54074d68e
20 changed files with 205 additions and 151 deletions
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compiler/pgates/pgate.py
-1
View File
@@ -216,4 +216,3 @@ class pgate(design.design):
# offset=implant_offset,
# width=implant_width,
# height=implant_height)
compiler/pgates/pinv.py
+15 -3
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@@ -62,7 +62,9 @@ class pinv(pgate.pgate):
def add_pins(self):
""" Adds pins for spice netlist """
self.add_pin_list(["A", "Z", "vdd", "gnd"])
pin_list = ["A", "Z", "vdd", "gnd"]
dir_list = ['INPUT', 'OUTPUT', 'POWER', 'GROUND']
self.add_pin_list(pin_list, dir_list)
def determine_tx_mults(self):
@@ -283,7 +285,8 @@ class pinv(pgate.pgate):
return transition_prob*(c_load + c_para)
def get_cin(self):
"""Return the capacitance of the gate connection in generic capacitive units relative to the minimum width of a transistor"""
"""Return the capacitance of the gate connection in generic capacitive
units relative to the minimum width of a transistor"""
return self.nmos_size + self.pmos_size
def get_stage_effort(self, cout, inp_is_rise=True):
@@ -291,4 +294,13 @@ class pinv(pgate.pgate):
Optional is_rise refers to the input direction rise/fall. Input inverted by this stage.
"""
parasitic_delay = 1
return logical_effort.logical_effort(self.name, self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise)
return logical_effort.logical_effort(self.name,
self.size,
self.get_cin(),
cout,
parasitic_delay,
not inp_is_rise)
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/pgates/pnand2.py
+8 -2
View File
@@ -33,7 +33,7 @@ class pnand2(pgate.pgate):
self.create_layout()
#For characterization purposes only
self.exclude_nmos_from_graph()
#self.exclude_nmos_from_graph()
def create_netlist(self):
self.add_pins()
@@ -54,7 +54,9 @@ class pnand2(pgate.pgate):
def add_pins(self):
""" Adds pins for spice netlist """
self.add_pin_list(["A", "B", "Z", "vdd", "gnd"])
pin_list = ["A", "B", "Z", "vdd", "gnd"]
dir_list = ['INPUT', 'INPUT', 'OUTPUT', 'POWER', 'GROUND']
self.add_pin_list(pin_list, dir_list)
def add_ptx(self):
@@ -268,3 +270,7 @@ class pnand2(pgate.pgate):
#Removing them simplifies generic path searching.
self.graph_inst_exclude.add(self.nmos1_inst)
self.graph_inst_exclude.add(self.nmos2_inst)
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/pgates/pnand3.py
+7 -1
View File
@@ -37,7 +37,9 @@ class pnand3(pgate.pgate):
def add_pins(self):
""" Adds pins for spice netlist """
self.add_pin_list(["A", "B", "C", "Z", "vdd", "gnd"])
pin_list = ["A", "B", "C", "Z", "vdd", "gnd"]
dir_list = ['INPUT', 'INPUT', 'INPUT', 'OUTPUT', 'POWER', 'GROUND']
self.add_pin_list(pin_list, dir_list)
def create_netlist(self):
self.add_pins()
@@ -272,3 +274,7 @@ class pnand3(pgate.pgate):
"""
parasitic_delay = 3
return logical_effort.logical_effort(self.name, self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise)
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/pgates/pnor2.py
+6 -1
View File
@@ -34,7 +34,9 @@ class pnor2(pgate.pgate):
def add_pins(self):
""" Adds pins for spice netlist """
self.add_pin_list(["A", "B", "Z", "vdd", "gnd"])
pin_list = ["A", "B", "Z", "vdd", "gnd"]
dir_list = ['INPUT', 'INPUT', 'OUTPUT', 'INOUT', 'INOUT']
self.add_pin_list(pin_list, dir_list)
def create_netlist(self):
self.add_pins()
@@ -234,3 +236,6 @@ class pnor2(pgate.pgate):
transition_prob = spice["nor2_transition_prob"]
return transition_prob*(c_load + c_para)
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/pgates/ptx.py
+9 -11
View File
@@ -60,7 +60,13 @@ class ptx(design.design):
#self.DRC()
def create_netlist(self):
self.add_pin_list(["D", "G", "S", "B"])
pin_list = ["D", "G", "S", "B"]
if self.tx_type=="nmos":
body_dir = 'GROUND'
else: #Assumed that the check for either pmos or nmos is done elsewhere.
body_dir = 'POWER'
dir_list = ['INOUT', 'INPUT', 'INOUT', body_dir]
self.add_pin_list(pin_list, dir_list)
# self.spice.append("\n.SUBCKT {0} {1}".format(self.name,
# " ".join(self.pins)))
@@ -358,14 +364,6 @@ class ptx(design.design):
return self.tx_width/drc("minwidth_tx")
def build_graph(self, graph, inst_name, port_nets):
"""Adds ptx edges to graph. Lowest graph level."""
#The ptx has four connections: (S)ource, (G)ate, (D)rain, (B)ody. The positions in spice
#are hardcoded which is represented here as well.
#Edges are connected as follows: G->S, G->D, D<->S. Body not represented in graph.
if len(port_nets) != 4:
debug.error("Transistor has non-standard connections.",1)
graph.add_edge(port_nets[1],port_nets[0])
graph.add_edge(port_nets[1],port_nets[2])
graph.add_edge(port_nets[0],port_nets[2])
graph.add_edge(port_nets[2],port_nets[0])
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)