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Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

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This commit is contained in:
Hunter Nichols
2019-05-07 00:52:27 -07:00
parent 5bfc42fdbb
commit d54074d68e
20 changed files with 205 additions and 151 deletions
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compiler/modules/dff.py
+4 -6
View File
@@ -11,6 +11,7 @@ class dff(design.design):
"""
pin_names = ["D", "Q", "clk", "vdd", "gnd"]
type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"])
@@ -20,6 +21,7 @@ class dff(design.design):
self.width = dff.width
self.height = dff.height
self.pin_map = dff.pin_map
self.add_pin_types(self.type_list)
def analytical_power(self, corner, load):
"""Returns dynamic and leakage power. Results in nW"""
@@ -51,10 +53,6 @@ class dff(design.design):
return parameter["dff_clk_cin"]
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Handmade cells must implement this manually."""
#The cell has 5 net ports hard-coded in self.pin_names. The edges
#are based on the hard-coded name positions.
# The edges added are: clk->Q.
# Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
graph.add_edge(port_nets[2],port_nets[1])
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/modules/sense_amp.py
+5 -9
View File
@@ -13,6 +13,7 @@ class sense_amp(design.design):
"""
pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"]
type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
@@ -23,7 +24,8 @@ class sense_amp(design.design):
self.width = sense_amp.width
self.height = sense_amp.height
self.pin_map = sense_amp.pin_map
self.add_pin_types(self.type_list)
def input_load(self):
#Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
from tech import spice, parameter
@@ -54,12 +56,6 @@ class sense_amp(design.design):
return 2*pmos_cin + nmos_cin
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Handmade cells must implement this manually."""
#The cell has 6 net ports hard-coded in self.pin_names. The edges
#are based on the hard-coded name positions.
# The edges added are: en->dout, bl->dout
# br->dout not included to reduce complexity
# Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
graph.add_edge(port_nets[0],port_nets[2])
graph.add_edge(port_nets[3],port_nets[2])
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/modules/tri_gate.py
+4 -9
View File
@@ -11,6 +11,7 @@ class tri_gate(design.design):
"""
pin_names = ["in", "out", "en", "en_bar", "gnd", "vdd"]
type_list = ["INPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("tri_gate", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "tri_gate", GDS["unit"])
@@ -26,6 +27,7 @@ class tri_gate(design.design):
self.width = tri_gate.width
self.height = tri_gate.height
self.pin_map = tri_gate.pin_map
self.add_pin_types(self.type_list)
def analytical_delay(self, corner, slew, load=0.0):
from tech import spice
@@ -43,12 +45,5 @@ class tri_gate(design.design):
return 9*spice["min_tx_gate_c"]
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Handmade cells must implement this manually."""
#The cell has 6 net ports hard-coded in self.pin_names. The edges
#are based on the hard-coded name positions.
# The edges added are: en->out, en_bar->out, in->out.
# A liberal amount of edges were added, may be reduced later for complexity.
# Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
graph.add_edge(port_nets[0],port_nets[1])
graph.add_edge(port_nets[2],port_nets[1])
graph.add_edge(port_nets[3],port_nets[1])
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
compiler/modules/write_driver.py
+5 -12
View File
@@ -11,7 +11,8 @@ class write_driver(design.design):
the technology library.
"""
pin_names = ["din", "bl", "br", "en", "gnd", "vdd"]
pin_names = ["din", "bl", "br", "en", "vdd", "gnd"]
type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
@@ -22,7 +23,7 @@ class write_driver(design.design):
self.width = write_driver.width
self.height = write_driver.height
self.pin_map = write_driver.pin_map
self.add_pin_types(self.type_list)
def get_w_en_cin(self):
"""Get the relative capacitance of a single input"""
@@ -30,13 +31,5 @@ class write_driver(design.design):
return 5*3
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Handmade cells must implement this manually."""
#The cell has 6 net ports hard-coded in self.pin_names. The edges
#are based on the hard-coded name positions.
# The edges added are: din->bl, din->br, en->bl, en->br
# A liberal amount of edges were added, may be reduced later for complexity.
# Internal nodes of the handmade cell not considered, only ports. vdd/gnd ignored for graph.
graph.add_edge(port_nets[0],port_nets[1])
graph.add_edge(port_nets[0],port_nets[2])
graph.add_edge(port_nets[3],port_nets[1])
graph.add_edge(port_nets[3],port_nets[2])
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)