Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

compiler/base/hierarchy_design.py

@@ -120,7 +120,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         #Translate port names to external nets
         if len(port_nets) != len(self.pins):
             debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1)
-        port_dict = {i:j for i,j in zip(self.pins, port_nets)}
+        port_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
         debug.info(3, "Instance name={}".format(inst_name))
         for subinst, conns in zip(self.insts, self.conns):
             if subinst in self.graph_inst_exclude:
@@ -139,6 +139,20 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
                 converted_conns.append("{}.{}".format(inst_name, conn))
         return converted_conns        
             
+    def add_graph_edges(self, graph, port_nets):
+        """For every input, adds an edge to every output.
+           Only intended to be used for gates and other simple modules."""
+        #The final pin names will depend on the spice hierarchy, so
+        #they are passed as an input.
+        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
+        input_pins = self.get_inputs()
+        output_pins = self.get_outputs()
+        inout_pins = self.get_inouts()
+        for inp in input_pins+inout_pins:
+            for out in output_pins+inout_pins:
+                if inp != out: #do not add self loops
+                    graph.add_edge(pin_dict[inp], pin_dict[out])        
+            
     def __str__(self):
         """ override print function output """
         return "design: " + self.name

compiler/base/hierarchy_spice.py

@@ -58,6 +58,17 @@ class spice():
         else:
             debug.error("Mismatch in type and pin list lengths.", -1)
 
+    def add_pin_types(self, type_list):
+        """Add pin types for all the cell's pins.
+           Typically, should only be used for handmade cells."""
+        #This only works if self.pins == bitcell.pin_names
+        if self.pin_names != self.pins:
+            debug.error("{} spice subcircuit port names do not match pin_names\
+                      \n SPICE names={}\
+                      \n Module names={}\
+                      ".format(self.name, self.pin_names, self.pins),1)         
+        self.pin_type = {pin:type for pin,type in zip(self.pin_names, type_list)}        
+            
     def get_pin_type(self, name):
         """ Returns the type of the signal pin. """
         return self.pin_type[name]
@@ -87,6 +98,14 @@ class spice():
                 output_list.append(pin)
         return output_list
 
+    def get_inouts(self):
+        """ These use pin types to determine pin lists. These
+        may be over-ridden by submodules that didn't use pin directions yet."""
+        inout_list = []
+        for pin in self.pins:
+            if self.pin_type[pin]=="INOUT":
+                inout_list.append(pin)
+        return inout_list
 
     def add_mod(self, mod):
         """Adds a subckt/submodule to the subckt hierarchy"""