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Update golden tests for verilog

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mrg
2021-05-06 19:56:22 -07:00
parent 57c58ce4a5
commit d43edd95e4
2 changed files with 0 additions and 2 deletions
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compiler/tests/golden/sram_2_16_1_freepdk45.v
-1
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@@ -19,7 +19,6 @@ module sram_2_16_1_freepdk45(
parameter VERBOSE = 1 ; //Set to 0 to only display warnings
parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
module sram_2_16_1_freepdk45(
`ifdef USE_POWER_PINS
inout vdd;
inout gnd;
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
-1
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@@ -19,7 +19,6 @@ module sram_2_16_1_scn4m_subm(
parameter VERBOSE = 1 ; //Set to 0 to only display warnings
parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
module sram_2_16_1_scn4m_subm(
`ifdef USE_POWER_PINS
inout vdd;
inout gnd;