mirror of https://github.com/VLSIDA/OpenRAM.git
pbitcell working with bitline adjustments
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parent
1062cbfd7f
commit
d42cd9a281
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@ -333,22 +333,22 @@ class instance(geometry):
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if node.mirror == 'MX':
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if node.mirror == 'MX':
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Q_y = -1 * Q_y
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Q_y = -1 * Q_y
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Q_bar_y = -1 * Q_bar_y
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Q_bar_y = -1 * Q_bar_y
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for pair in range(len(normalized_bl_offsets)):
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for pair in range(len(normalized_bl_offsets)):
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for offset in range(len(offset)):
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normalized_bl_offsets[pair] = (normalized_bl_offsets[pair][0],
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normalized_bl_offsets[pair][offset] = -1 * normalized_bl_offsets[pair][offset]
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-1 * normalized_bl_offsets[pair][1])
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for pair in range(len(normalized_br_offsets)):
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for pair in range(len(normalized_br_offsets)):
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for offset in range(len(offset)):
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normalized_br_offsets[pair] = (normalized_br_offsets[pair][0],
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normalized_br_offsets[pair][offset] = -1 * normalized_br_offsets[pair][offset]
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-1 * normalized_br_offsets[pair][1])
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Q_offsets.append([Q_x, Q_y])
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Q_offsets.append([Q_x, Q_y])
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Q_bar_offsets.append([Q_bar_x, Q_bar_y])
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Q_bar_offsets.append([Q_bar_x, Q_bar_y])
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for offset in bl_offset:
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bl_offsets.append(offset)
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bl_offsets.append(normalized_bl_offsets)
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for offset in br.offset:
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br_offsets.append(normalized_br_offsets)
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br_offsets.append(offset)
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elif node.mod.insts is not []:
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elif node.mod.insts is not []:
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for instance in node.mod.insts:
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for instance in node.mod.insts:
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@ -63,10 +63,6 @@ class stimuli():
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self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
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self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
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self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
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self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
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for col in range(OPTS.word_size):
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for col in range(OPTS.word_size):
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if OPTS.num_banks == 1:
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self.sf.write("bl_{2} ".format(bank, row,col))
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self.sf.write("br_{2} ".format(bank, row,col))
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else:
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self.sf.write("bl{0}_{2} ".format(bank, row,col))
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self.sf.write("bl{0}_{2} ".format(bank, row,col))
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self.sf.write("br{0}_{2} ".format(bank, row,col))
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self.sf.write("br{0}_{2} ".format(bank, row,col))
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@ -19,6 +19,7 @@ from verilog import verilog
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from lef import lef
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from lef import lef
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from sram_factory import factory
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from sram_factory import factory
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from tech import drc
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from tech import drc
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import numpy as np
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import logical_effort
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import logical_effort
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class sram_base(design, verilog, lef):
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class sram_base(design, verilog, lef):
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@ -102,33 +103,38 @@ class sram_base(design, verilog, lef):
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bl_offsets = pex_offsets[3]
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bl_offsets = pex_offsets[3]
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br_offsets = pex_offsets[4]
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br_offsets = pex_offsets[4]
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storage_layer_name = "metal1"
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bitline_layer_name = "metal2"
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Q = [bank_offset[bank_num][0] + Q_offset[bank_num][0], bank_offset[bank_num][1] + Q_offset[bank_num][1]]
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Q_bar = [bank_offset[bank_num][0] + Q_bar_offset[bank_num][0], bank_offset[bank_num][1] + Q_bar_offset[bank_num][1]]
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bl = []
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bl = []
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br = []
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br = []
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for i in range(len(bl_offsets)):
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storage_layer_name = "metal1"
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bl.append([bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)+1]])
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bitline_layer_name = "metal2"
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for i in range(len(br_offsets)):
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for cell in range(len(bank_offset)):
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br.append([bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)+1]])
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Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
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Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
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self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
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self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q)
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self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
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self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar)
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for bitline in range(len(bl_offsets[cell])):
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bitline_location = [float(bank_offset[cell][0]) + bl_offsets[cell][bitline][0], float(bank_offset[cell][1]) + bl_offsets[cell][bitline][1]]
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bl.append(bitline_location)
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for bitline in range(len(br_offsets[0])):
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bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]]
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br.append(bitline_location)
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for col in range(len(bl)):
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if OPTS.num_banks == 1:
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if OPTS.num_banks == 1:
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for i in range(len(bl_offsets)):
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self.add_layout_pin_rect_center("bl0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, bl[col])
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self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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for i in range(len(br_offsets)):
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self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
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else:
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else:
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self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
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for col in range(len(br)):
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if OPTS.num_banks == 1:
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self.add_layout_pin_rect_center("br0_{0}".format(int(col / OPTS.num_words)), bitline_layer_name, br[col])
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else:
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self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, br)
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@ -420,10 +420,6 @@ def correct_port(name, output_file_name, ref_file_name):
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
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for col in range(OPTS.word_size):
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for col in range(OPTS.word_size):
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if OPTS.num_banks == 1:
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bitcell_list += "bl_{2} ".format(bank, row,col)
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bitcell_list += "br_{2} ".format(bank, row,col)
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else:
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bitcell_list += "bl{0}_{2} ".format(bank, row,col)
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bitcell_list += "bl{0}_{2} ".format(bank, row,col)
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bitcell_list += "br{0}_{2} ".format(bank, row,col)
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bitcell_list += "br{0}_{2} ".format(bank, row,col)
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bitcell_list += "\n"
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bitcell_list += "\n"
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