diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index f8987339..5dd0327a 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -214,9 +214,14 @@ class cell_properties():
         self._col_cap_1port_bitcell = _cell(["bl", "br", "vdd", "gnd"],
                                             ["OUTPUT", "OUTPUT", "POWER", "GROUND"])
 
-        self._col_cap_1port_strap = _cell(["vdd", "gnd"],
-                                          ["POWER", "GROUND"])
+        self._col_cap_1port_strap_power = _cell(["vdd"],
+                                                ["POWER"])
 
+        self._col_cap_1port_strap_ground = _cell(["gnd"],
+                                                 ["GROUND"])
+
+        self._row_cap_1port_cell = _cell(['vdd]'],
+                                         ['POWRER'])
 
         self._row_cap_1port = _bitcell(["wl", "gnd"],
                                        ["INPUT", "POWER", "GROUND"])
@@ -280,8 +285,16 @@ class cell_properties():
         return self._col_cap_1port_bitcell
 
     @property
-    def col_cap_1port_strap(self):
-        return self._col_cap_1port_strap
+    def col_cap_1port_strap_power(self):
+        return self._col_cap_1port_strap_power
+
+    @property
+    def col_cap_1port_strap_ground(self):
+        return self._col_cap_1port_strap_ground
+
+    @property
+    def row_cap_1port_cell(self):
+        return self._row_cap_1port_cell
 
     @property
     def row_cap_1port(self):