mirror of https://github.com/VLSIDA/OpenRAM.git
Use local setup.tcl and flatten bitcell arrays.
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@ -97,10 +97,11 @@ def write_netgen_script(cell_name, sp_name):
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global OPTS
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global OPTS
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setup_file = OPTS.openram_tech + "mag_lib/setup.tcl"
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setup_file = "setup.tcl"
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if os.path.exists(setup_file):
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full_setup_file = OPTS.openram_tech + "mag_lib/" + setup_file
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if os.path.exists(full_setup_file):
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# Copy setup.tcl file into temp dir
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# Copy setup.tcl file into temp dir
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shutil.copy(setup_file, OPTS.openram_temp)
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shutil.copy(full_setup_file, OPTS.openram_temp)
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else:
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else:
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setup_file = 'nosetup'
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setup_file = 'nosetup'
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@ -4,8 +4,8 @@ equate class {-circuit1 nfet} {-circuit2 n}
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equate class {-circuit1 pfet} {-circuit2 p}
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equate class {-circuit1 pfet} {-circuit2 p}
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# This circuit has symmetries and needs to be flattened to resolve them
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# This circuit has symmetries and needs to be flattened to resolve them
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# or the banks won't pass
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# or the banks won't pass
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#flatten class {-circuit1 bitcell_array_0}
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flatten class {-circuit1 bitcell_array_0}
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#flatten class {-circuit1 bitcell_array_1}
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flatten class {-circuit1 bitcell_array_1}
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#flatten class {-circuit1 precharge_array_0}
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#flatten class {-circuit1 precharge_array_0}
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#flatten class {-circuit1 precharge_array_1}
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#flatten class {-circuit1 precharge_array_1}
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#flatten class {-circuit1 precharge_array_2}
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#flatten class {-circuit1 precharge_array_2}
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