mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-08 12:03:27 +02:00
Reapply jsowash update without spice model file
This commit is contained in:
@@ -1,10 +1,10 @@
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library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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voltage_unit : "1V" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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@@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){
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area : 1124.88;
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leakage_power () {
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when : "CSb0";
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when : "csb0";
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value : 0.000167;
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}
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cell_leakage_power : 0;
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@@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(CSb0){
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pin(csb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(WEb0){
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pin(web0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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when : "!csb0 & clk0 & !web0";
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rise_power(scalar){
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values("0.033101244168888884");
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}
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@@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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when : "!csb0 & !clk0 & web0";
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rise_power(scalar){
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values("0.033101244168888884");
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}
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@@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "CSb0";
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when : "csb0";
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rise_power(scalar){
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values("0");
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}
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@@ -1,10 +1,10 @@
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library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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voltage_unit : "1V" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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@@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){
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area : 1124.88;
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leakage_power () {
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when : "CSb0";
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when : "csb0";
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value : 0.000167;
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}
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cell_leakage_power : 0;
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@@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(CSb0){
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pin(csb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(WEb0){
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pin(web0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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when : "!csb0 & clk0 & !web0";
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rise_power(scalar){
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values("0.033101244168888884");
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}
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@@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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when : "!csb0 & !clk0 & web0";
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rise_power(scalar){
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values("0.033101244168888884");
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}
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@@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "CSb0";
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when : "csb0";
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rise_power(scalar){
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values("0");
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}
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@@ -1,10 +1,10 @@
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library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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voltage_unit : "1V" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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@@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){
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area : 977.4951374999999;
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leakage_power () {
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when : "CSb0";
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when : "csb0";
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value : 0.0011164579999999999;
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}
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cell_leakage_power : 0;
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@@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(CSb0){
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pin(csb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(WEb0){
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pin(web0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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when : "!csb0 & clk0 & !web0";
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rise_power(scalar){
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values("0.03599689694444445");
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}
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@@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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when : "!csb0 & !clk0 & web0";
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rise_power(scalar){
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values("0.029906643888888886");
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}
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@@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "CSb0";
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when : "csb0";
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rise_power(scalar){
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values("0");
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}
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@@ -1,10 +1,10 @@
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library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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voltage_unit : "1V" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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@@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){
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area : 977.4951374999999;
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leakage_power () {
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when : "CSb0";
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when : "csb0";
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value : 0.000179;
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}
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cell_leakage_power : 0;
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@@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(CSb0){
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pin(csb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(WEb0){
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pin(web0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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when : "!csb0 & clk0 & !web0";
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rise_power(scalar){
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values("0.0747594982142222");
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}
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@@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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when : "!csb0 & !clk0 & web0";
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rise_power(scalar){
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values("0.0747594982142222");
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}
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@@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "CSb0";
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when : "csb0";
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rise_power(scalar){
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values("0");
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}
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@@ -1,10 +1,10 @@
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library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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voltage_unit : "1V" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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@@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){
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area : 977.4951374999999;
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leakage_power () {
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when : "CSb0";
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when : "csb0";
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value : 0.0011164579999999999;
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}
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cell_leakage_power : 0;
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@@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(CSb0){
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pin(csb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(WEb0){
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pin(web0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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@@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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when : "!csb0 & clk0 & !web0";
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rise_power(scalar){
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values("0.03334771594444444");
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}
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@@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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when : "!csb0 & !clk0 & web0";
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rise_power(scalar){
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values("0.028457026222222223");
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}
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@@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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internal_power(){
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when : "CSb0";
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when : "csb0";
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rise_power(scalar){
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values("0");
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}
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@@ -1,10 +1,10 @@
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library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
|
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voltage_unit : "1v" ;
|
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voltage_unit : "1V" ;
|
||||
current_unit : "1mA" ;
|
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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capacitive_load_unit(1, pF) ;
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leakage_power_unit : "1mW" ;
|
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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@@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
area : 73068.14000000001;
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leakage_power () {
|
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when : "CSb0";
|
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when : "csb0";
|
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value : 0.000167;
|
||||
}
|
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cell_leakage_power : 0;
|
||||
@@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
pin(csb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
pin(web0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
when : "!csb0 & clk0 & !web0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
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||||
}
|
||||
@@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
when : "!csb0 & !clk0 & web0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
@@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
voltage_unit : "1V" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
capacitive_load_unit(1, pF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
@@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
area : 73068.14000000001;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
value : 0.000167;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
@@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
pin(csb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
pin(web0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
when : "!csb0 & clk0 & !web0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
@@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
when : "!csb0 & !clk0 & web0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
@@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
voltage_unit : "1V" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
capacitive_load_unit(1, pF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
@@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
value : 0.0009813788999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
@@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
pin(csb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
pin(web0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
when : "!csb0 & clk0 & !web0";
|
||||
rise_power(scalar){
|
||||
values("9.972790277777777");
|
||||
}
|
||||
@@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
when : "!csb0 & !clk0 & web0";
|
||||
rise_power(scalar){
|
||||
values("8.899322499999998");
|
||||
}
|
||||
@@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
voltage_unit : "1V" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
capacitive_load_unit(1, pF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
@@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
value : 0.000179;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
@@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
pin(csb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
pin(web0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
when : "!csb0 & clk0 & !web0";
|
||||
rise_power(scalar){
|
||||
values("11.3049604371");
|
||||
}
|
||||
@@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
when : "!csb0 & !clk0 & web0";
|
||||
rise_power(scalar){
|
||||
values("11.3049604371");
|
||||
}
|
||||
@@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
voltage_unit : "1V" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
capacitive_load_unit(1, pF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
@@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
value : 0.0009813788999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
@@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
pin(csb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
pin(web0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
@@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
when : "!csb0 & clk0 & !web0";
|
||||
rise_power(scalar){
|
||||
values("9.602821763527778");
|
||||
}
|
||||
@@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
when : "!csb0 & !clk0 & web0";
|
||||
rise_power(scalar){
|
||||
values("8.647938152416664");
|
||||
}
|
||||
@@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
when : "csb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user