From d22d7de1950eb93ccac1c701559ff63076a6a3a3 Mon Sep 17 00:00:00 2001 From: Matt Date: Mon, 24 Jun 2019 08:59:58 -0700 Subject: [PATCH] Reapply jsowash update without spice model file --- compiler/base/geometry.py | 23 ++++--- compiler/base/lef.py | 21 ++---- compiler/characterizer/lib.py | 66 ++++++++++--------- compiler/gdsMill/gdsMill/vlsiLayout.py | 17 ++++- ..._16_1_freepdk45_FF_1p0V_25C_analytical.lib | 16 ++--- ..._16_1_freepdk45_SS_1p0V_25C_analytical.lib | 16 ++--- .../sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 16 ++--- ..._16_1_freepdk45_TT_1p0V_25C_analytical.lib | 16 ++--- ...am_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 16 ++--- ...16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 16 ++--- ...16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 16 ++--- .../sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 16 ++--- ...16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 16 ++--- ...m_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 16 ++--- 14 files changed, 149 insertions(+), 138 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index ddff6049..56bae83d 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -183,21 +183,20 @@ class instance(geometry): elif self.mirror=="XY": mirr = 1 angle += math.radians(180.0) - - if self.mod.is_library_cell: - # For lib cells, block the whole thing except on metal3 - # since they shouldn't use metal3 - if layer==tech.layer["metal1"] or layer==tech.layer["metal2"]: - return [self.transform_coords(self.mod.get_boundary(), self.offset, mirr, angle)] - else: - return [] - else: - blockages = self.mod.get_blockages(layer) - new_blockages = [] + new_blockages = [] + if self.mod.is_library_cell: + blockages = [] + blockages = self.mod.gds.getBlockages(layer) for b in blockages: new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) - return new_blockages + print(new_blockages) + else: + blockages = self.mod.get_blockages(layer) + for b in blockages: + new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) + return new_blockages + def gds_write_file(self, new_layout): """Recursively writes all the sub-modules in this instance""" diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 5bc76bb0..ea2ff5ad 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -21,9 +21,11 @@ class lef: """ def __init__(self,layers): # LEF db units per micron - self.lef_units = 1000 + self.lef_units = 2000 # These are the layers of the obstructions self.lef_layers = layers + # Round to ensure float values are divisible by 0.0025 (the manufacturing grid) + self.round_grid = 4; def lef_write(self, lef_name): """Write the entire lef of the object to the file.""" @@ -48,25 +50,14 @@ class lef: self.lef.write("UNITS\n") self.lef.write(" DATABASE MICRONS {0} ;\n".format(self.lef_units)) self.lef.write("END UNITS\n") - - self.lef.write("SITE MacroSite\n") - self.indent += " " - self.lef.write("{0}CLASS Core ;\n".format(self.indent)) - self.lef.write("{0}SIZE {1} by {2} ;\n".format(self.indent, - self.lef_units*self.width, - self.lef_units*self.height)) - self.indent = self.indent[:-3] - self.lef.write("END MacroSite\n") self.lef.write("{0}MACRO {1}\n".format(self.indent,self.name)) self.indent += " " self.lef.write("{0}CLASS BLOCK ;\n".format(self.indent)) self.lef.write("{0}SIZE {1} BY {2} ;\n" .format(self.indent, - self.lef_units*self.width, - self.lef_units*self.height)) + round(self.width,self.round_grid), + round(self.height,self.round_grid))) self.lef.write("{0}SYMMETRY X Y R90 ;\n".format(self.indent)) - self.lef.write("{0}SITE MacroSite ;\n".format(self.indent)) - def lef_write_footer(self): self.lef.write("{0}END {1}\n".format(self.indent,self.name)) @@ -119,5 +110,5 @@ class lef: """ Write a LEF rectangle """ self.lef.write("{0}RECT ".format(self.indent)) for item in rect: - self.lef.write(" {0} {1}".format(self.lef_units*item[0], self.lef_units*item[1])) + self.lef.write(" {0} {1}".format(round(item[0],self.round_grid), round(item[1],self.round_grid))) self.lef.write(" ;\n") diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 6e47e5cc..747e9869 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -148,9 +148,9 @@ class lib: self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height)) #Build string of all control signals. - control_str = 'CSb0' #assume at least 1 port + control_str = 'csb0' #assume at least 1 port for i in range(1, self.total_port_num): - control_str += ' & CSb{0}'.format(i) + control_str += ' & csb{0}'.format(i) # Leakage is included in dynamic when macro is enabled self.lib.write(" leakage_power () {\n") @@ -161,13 +161,17 @@ class lib: def write_units(self): - """ Adds default units for time, voltage, current,...""" - + """ Adds default units for time, voltage, current,... + Valid values are 1mV, 10mV, 100mV, and 1V. + For time: Valid values are 1ps, 10ps, 100ps, and 1ns. + For power: Valid values are 1mW, 100uW (for 100mW), 10uW (for 10mW), + 1uW (for 1mW), 100nW, 10nW, 1nW, 100pW, 10pW, and 1pW. + """ self.lib.write(" time_unit : \"1ns\" ;\n") - self.lib.write(" voltage_unit : \"1v\" ;\n") + self.lib.write(" voltage_unit : \"1V\" ;\n") self.lib.write(" current_unit : \"1mA\" ;\n") self.lib.write(" resistance_unit : \"1kohm\" ;\n") - self.lib.write(" capacitive_load_unit(1 ,fF) ;\n") + self.lib.write(" capacitive_load_unit(1, pF) ;\n") self.lib.write(" leakage_power_unit : \"1mW\" ;\n") self.lib.write(" pulling_resistance_unit :\"1kohm\" ;\n") self.lib.write(" operating_conditions(OC){\n") @@ -239,7 +243,9 @@ class lib: self.lib.write(" variable_1 : input_net_transition;\n") self.lib.write(" variable_2 : total_output_net_capacitance;\n") self.write_index(1,self.slews) - self.write_index(2,self.loads) + # Dividing by 1000 to all cap values since output of .sp is in fF, + # and it needs to be in pF for Innovus. + self.write_index(2,self.loads/1000) self.lib.write(" }\n\n") CONS = ["CONSTRAINT_TABLE"] @@ -327,8 +333,8 @@ class lib: self.lib.write(" bus_type : DATA; \n") self.lib.write(" direction : output; \n") # This is conservative, but limit to range that we characterized. - self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads))) - self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads))) + self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads)/1000)) + self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads)/1000)) self.lib.write(" memory_read(){ \n") self.lib.write(" address : ADDR{0}; \n".format(read_port)) self.lib.write(" }\n") @@ -362,7 +368,7 @@ class lib: self.lib.write(" bus_type : DATA; \n") self.lib.write(" direction : input; \n") # This is conservative, but limit to range that we characterized. - self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) + self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000)) self.lib.write(" memory_write(){ \n") self.lib.write(" address : ADDR{0}; \n".format(write_port)) self.lib.write(" clocked_on : clk{0}; \n".format(write_port)) @@ -385,7 +391,7 @@ class lib: self.lib.write(" bus(ADDR{0}){{\n".format(port)) self.lib.write(" bus_type : ADDR; \n") self.lib.write(" direction : input; \n") - self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) + self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000)) self.lib.write(" max_transition : {0};\n".format(self.slews[-1])) self.lib.write(" pin(ADDR{0}[{1}:0])".format(port,self.sram.addr_size-1)) self.lib.write("{\n") @@ -398,15 +404,15 @@ class lib: def write_control_pins(self, port): """ Adds control pins timing results.""" #The control pins are still to be determined. This is a placeholder for what could be. - ctrl_pin_names = ["CSb{0}".format(port)] + ctrl_pin_names = ["csb{0}".format(port)] if port in self.readwrite_ports: - ctrl_pin_names.append("WEb{0}".format(port)) + ctrl_pin_names.append("web{0}".format(port)) for i in ctrl_pin_names: self.lib.write(" pin({0})".format(i)) self.lib.write("{\n") self.lib.write(" direction : input; \n") - self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) + self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000)) self.write_FF_setuphold(port) self.lib.write(" }\n\n") @@ -417,7 +423,7 @@ class lib: self.lib.write(" clock : true;\n") self.lib.write(" direction : input; \n") # FIXME: This depends on the clock buffer size in the control logic - self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) + self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]/1000)) self.add_clk_control_power(port) @@ -452,10 +458,10 @@ class lib: if port in self.write_ports: if port in self.read_ports: - web_name = " & !WEb{0}".format(port) + web_name = " & !web{0}".format(port) avg_write_power = np.mean(self.char_port_results[port]["write1_power"] + self.char_port_results[port]["write0_power"]) self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!CSb{0} & clk{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" when : \"!csb{0} & clk{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) self.lib.write(" }\n") @@ -466,10 +472,10 @@ class lib: if port in self.read_ports: if port in self.write_ports: - web_name = " & WEb{0}".format(port) + web_name = " & web{0}".format(port) avg_read_power = np.mean(self.char_port_results[port]["read1_power"] + self.char_port_results[port]["read0_power"]) self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!CSb{0} & !clk{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" when : \"!csb{0} & !clk{0}{1}\"; \n".format(port, web_name)) self.lib.write(" rise_power(scalar){\n") self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) self.lib.write(" }\n") @@ -480,7 +486,7 @@ class lib: # Have 0 internal power when disabled, this will be represented as leakage power. self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"CSb{0}\"; \n".format(port)) + self.lib.write(" when : \"csb{0}\"; \n".format(port)) self.lib.write(" rise_power(scalar){\n") self.lib.write(" values(\"0\");\n") self.lib.write(" }\n") @@ -610,9 +616,9 @@ class lib: )) for port in self.all_ports: - #CSb timings + #csb timings datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( - "CSb{0}".format(port), + "csb{0}".format(port), min(list(map(round_time,self.times["setup_times_LH"]))), max(list(map(round_time,self.times["setup_times_LH"]))), @@ -649,9 +655,9 @@ class lib: for port in self.all_ports: if port in self.readwrite_ports: - #WEb timings + #web timings datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( - "WEb{0}".format(port), + "web{0}".format(port), min(list(map(round_time,self.times["setup_times_LH"]))), max(list(map(round_time,self.times["setup_times_LH"]))), @@ -673,8 +679,8 @@ class lib: # write dynamic power usage if port in self.read_ports: - web_name = " & !WEb{0}".format(port) - name = "!CSb{0} & clk{0}{1}".format(port, web_name) + web_name = " & !web{0}".format(port) + name = "!csb{0} & clk{0}{1}".format(port, web_name) read_write = 'Read' datasheet.write("{0},{1},{2},{3},".format( @@ -686,8 +692,8 @@ class lib: )) if port in self.write_ports: - web_name = " & WEb{0}".format(port) - name = "!CSb{0} & !clk{0}{1}".format(port, web_name) + web_name = " & web{0}".format(port) + name = "!csb{0} & !clk{0}{1}".format(port, web_name) read_write = 'Write' datasheet.write("{0},{1},{2},{3},".format( @@ -699,9 +705,9 @@ class lib: )) # write leakage power - control_str = 'CSb0' + control_str = 'csb0' for i in range(1, self.total_port_num): - control_str += ' & CSb{0}'.format(i) + control_str += ' & csb{0}'.format(i) datasheet.write("{0},{1},{2},".format('leak', control_str, self.char_sram_results["leakage_power"])) diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index 03873ed4..992e3d26 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -2,6 +2,8 @@ from .gdsPrimitives import * from datetime import * #from mpmath import matrix #from numpy import matrix +from vector import vector +from pin_layout import pin_layout import numpy as np #import gdsPrimitives import debug @@ -729,7 +731,7 @@ class VlsiLayout: def getAllShapes(self,layer): """ - Return all gshapes on a given layer in [llx, lly, urx, ury] format and + Return all shapes on a given layer in [llx, lly, urx, ury] format and user units. """ boundaries = set() @@ -746,6 +748,19 @@ class VlsiLayout: return user_boundaries + def getBlockages(self,layer): + blockages = [] + + shapes = self.getAllShapes(layer) + for boundary in shapes: + ll = vector(boundary[0],boundary[1]) + ur = vector(boundary[2],boundary[3]) + rect = [ll,ur] + new_pin = rect + blockages.append(new_pin) + return blockages + + def getShapesInStructure(self,layer,structure): """ Go through all the shapes in a structure and return the list of shapes in diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index 88b54eca..48133f90 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){ area : 1124.88; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.000167; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 0.2091; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 0.2091; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("0.033101244168888884"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("0.033101244168888884"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index e78fe8d3..59b51dfd 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){ area : 1124.88; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.000167; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 0.2091; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 0.2091; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("0.033101244168888884"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("0.033101244168888884"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index 0939b4bb..6b2723a0 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){ area : 977.4951374999999; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.0011164579999999999; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 0.2091; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 0.2091; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("0.03599689694444445"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("0.029906643888888886"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index a06ff5b5..4708c2ef 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){ area : 977.4951374999999; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.000179; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 0.2091; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 0.2091; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("0.0747594982142222"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("0.0747594982142222"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index d7d7de7e..dbd7e03b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_freepdk45){ area : 977.4951374999999; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.0011164579999999999; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 0.2091; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_freepdk45){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 0.2091; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_freepdk45){ direction : input; capacitance : 0.2091; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("0.03334771594444444"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("0.028457026222222223"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_freepdk45){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index 5cbecd94..eef7df1b 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){ area : 73068.14000000001; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.000167; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 9.8242; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 9.8242; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("4.99880645"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("4.99880645"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index 3324f119..2f5c534c 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){ area : 73068.14000000001; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.000167; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 9.8242; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 9.8242; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("4.99880645"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("4.99880645"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index f8a337d3..943f2ecc 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){ area : 60774.3; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.0009813788999999999; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 9.8242; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 9.8242; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("9.972790277777777"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("8.899322499999998"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 72a106ac..4f98380c 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){ area : 60774.3; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.000179; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 9.8242; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 9.8242; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("11.3049604371"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("11.3049604371"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); } diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 124f80ff..b601f3b0 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -1,10 +1,10 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ delay_model : "table_lookup"; time_unit : "1ns" ; - voltage_unit : "1v" ; + voltage_unit : "1V" ; current_unit : "1mA" ; resistance_unit : "1kohm" ; - capacitive_load_unit(1 ,fF) ; + capacitive_load_unit(1, pF) ; leakage_power_unit : "1mW" ; pulling_resistance_unit :"1kohm" ; operating_conditions(OC){ @@ -81,7 +81,7 @@ cell (sram_2_16_1_scn4m_subm){ area : 60774.3; leakage_power () { - when : "CSb0"; + when : "csb0"; value : 0.0009813788999999999; } cell_leakage_power : 0; @@ -198,7 +198,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(CSb0){ + pin(csb0){ direction : input; capacitance : 9.8242; timing(){ @@ -231,7 +231,7 @@ cell (sram_2_16_1_scn4m_subm){ } } - pin(WEb0){ + pin(web0){ direction : input; capacitance : 9.8242; timing(){ @@ -269,7 +269,7 @@ cell (sram_2_16_1_scn4m_subm){ direction : input; capacitance : 9.8242; internal_power(){ - when : "!CSb0 & clk0 & !WEb0"; + when : "!csb0 & clk0 & !web0"; rise_power(scalar){ values("9.602821763527778"); } @@ -278,7 +278,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "!CSb0 & !clk0 & WEb0"; + when : "!csb0 & !clk0 & web0"; rise_power(scalar){ values("8.647938152416664"); } @@ -287,7 +287,7 @@ cell (sram_2_16_1_scn4m_subm){ } } internal_power(){ - when : "CSb0"; + when : "csb0"; rise_power(scalar){ values("0"); }