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single port progess

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This commit is contained in:
jcirimel
2020-09-14 18:11:38 -07:00
parent 73443c8c95
commit d22164bd48
129 changed files with 234723 additions and 77 deletions
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compiler/tests/05_bitcell_array_test.py
+2 -2
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@@ -23,8 +23,8 @@ class array_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing 4x4 array for 6t_cell")
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
debug.info(2, "Testing 8x8 array for 6t_cell")
a = factory.create(module_type="bitcell_array", cols=8, rows=8)
self.local_check(a)
globals.end_openram()