luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 11:08:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

single port progess

Browse Source
This commit is contained in:
jcirimel
2020-09-14 18:11:38 -07:00
parent 73443c8c95
commit d22164bd48
129 changed files with 234723 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/replica_bitcell_array.py
+1 -1
View File
@@ -88,7 +88,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
^ dummy columns ^
1 x (rows + 4)
"""
# Bitcell array
self.bitcell_array = factory.create(module_type="bitcell_array",
column_offset=1 + self.add_left_rbl,
@@ -109,6 +108,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
replica_bit = self.left_rbl + self.row_size + 1 + bit
# If we have an odd numer on the bottom
column_offset = self.left_rbl + 1
self.replica_columns[bit] = factory.create(module_type="replica_column",
rows=self.row_size,
rbl=self.rbl,