mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-01 18:48:10 +02:00
single port progess
This commit is contained in:
jcirimel
@@ -6,6 +6,7 @@
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# All rights reserved.
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#
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from bitcell_base_array import bitcell_base_array
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from s8_corner import s8_corner
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from tech import drc, spice
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from globals import OPTS
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from sram_factory import factory
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@@ -45,8 +46,29 @@ class bitcell_array(bitcell_base_array):
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def add_modules(self):
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""" Add the modules used in this design """
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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if OPTS.tech_name != "sky130":
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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else:
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#self.add_mod(factory.create(module_type="s8_corner", location = "ul"))
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#self.add_mod(factory.create(module_type="s8_corner", location = "ur"))
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#self.add_mod(factory.create(module_type="s8_corner", location = "ll"))
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#self.add_mod(factory.create(module_type="s8_corner", location = "lr"))
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#self.add_mod(factory.create(module_type="s8_col_end", version = "colenda"))
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#self.add_mod(factory.create(module_type="s8_col_end", version = "colenda"))
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#self.add_mod(factory.create(module_type="s8_col_end", version = "colend_p_cent"))
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#self.add_mod(factory.create(module_type="s8_col_end", version = "colenda_p_cent"))
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self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1"))
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self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1a"))
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
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self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
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def create_instances(self):
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""" Create the module instances used in this design """
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@@ -9,6 +9,7 @@ import debug
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import design
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from tech import cell_properties
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from sram_factory import factory
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from globals import OPTS
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class bitcell_base_array(design.design):
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@@ -25,8 +26,14 @@ class bitcell_base_array(design.design):
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self.column_offset = column_offset
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# Bitcell for port names only
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self.cell = factory.create(module_type="bitcell")
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if OPTS.tech_name != "sky130":
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self.cell = factory.create(module_type="bitcell")
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else:
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self.cell = factory.create(module_type="s8_bitcell", version="opt1")
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self.cell2 = factory.create(module_type="s8_bitcell", version="opt1a")
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self.strap = factory.create(module_type="s8_internal", version="wlstrap")
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self.strap2 = factory.create(module_type="s8_internal", version="wlstrap_p")
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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@@ -49,7 +56,11 @@ class bitcell_base_array(design.design):
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self.wordline_names = [[] for port in self.all_ports]
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for row in range(self.row_size):
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for port in self.all_ports:
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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if not cell_properties.bitcell.split_wl:
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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else:
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self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
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self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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def get_bitline_names(self, port=None):
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@@ -65,13 +76,20 @@ class bitcell_base_array(design.design):
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return self.wordline_names[port]
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def add_pins(self):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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if OPTS.tech_name != "sky130":
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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else:
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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def get_bitcell_pins(self, row, col):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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@@ -86,40 +104,78 @@ class bitcell_base_array(design.design):
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def add_layout_pins(self):
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""" Add the layout pins """
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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if OPTS.tech_name != "sky130":
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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else:
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl0_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="bl1_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl0_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl0_{0}_{1}".format(port, row),
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layer=wl0_pin.layer,
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offset=wl0_pin.ll().scale(0, 1),
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width=self.width,
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height=wl0_pin.height())
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wl1_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl1_{0}_{1}".format(port, row),
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layer=wl1_pin.layer,
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offset=wl1_pin.ll().scale(0, 1),
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width=self.width,
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height=wl1_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vpwr", "vgnd"]:
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self.copy_layout_pin(inst, pin_name)
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def _adjust_x_offset(self, xoffset, col, col_offset):
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tempx = xoffset
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dir_y = False
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@@ -140,27 +196,66 @@ class bitcell_base_array(design.design):
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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if OPTS.tech_name != "sky130":
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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else:
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array_layout = []
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for y in range(0,self.row_size):
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row_layout = []
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alternate_bitcell = 1
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alternate_strap = 1
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for x in range(0,self.column_size):
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if alternate_bitcell == 1:
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row_layout.append(self.cell)
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alternate_bitcell = 0
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else:
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row_layout.append(self.cell2)
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alternate_bitcell = 1
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if x != self.column_size:
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if alternate_strap:
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row_layout.append(self.strap2)
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alternate_strap = 0
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else:
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row_layout.append(self.strap)
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alternate_strap = 1
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array_layout.append(row_layout)
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self.height = self.row_size * self.cell.height + (self.row_size - 1) * self.strap.height
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self.width = self.column_size * self.cell.width + (self.column_size-1) * self.strap.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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for row in range(0, len(array_layout)):
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xoffset = 0.0
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for col in range(0, len(array_layout[row])):
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inst = self.add_inst(name = "row_{}, col_{}".format(row,col), mod=array_layout[row][col])
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inst.place(offset=[xoffset, yoffset])
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xoffset += inst.width
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yoffset += self.cell.height
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xoffset += self.cell.width
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@@ -0,0 +1,271 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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from tech import drc
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class custom_cell(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, pins, mod):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.column_offset = column_offset
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self.words_per_row = int(columns / word_size)
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if not num_spare_cols:
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self.num_spare_cols = 0
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else:
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self.num_spare_cols = num_spare_cols
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if self.write_size:
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self.num_wmasks = int(self.word_size / self.write_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def get_bl_name(self):
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bl_name = "bl"
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return bl_name
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def get_br_name(self):
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br_name = "br"
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return br_name
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@property
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def data_name(self):
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return "data"
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@property
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def en_name(self):
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return "en"
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_write_array()
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def create_layout(self):
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if self.bitcell.width > self.driver.width:
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self.width = (self.columns + self.num_spare_cols) * self.bitcell.width
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self.width_regular_cols = self.columns * self.bitcell.width
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self.single_col_width = self.bitcell.width
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else:
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self.width = (self.columns + self.num_spare_cols) * self.driver.width
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self.width_regular_cols = self.columns * self.driver.width
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self.single_col_width = self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(self.word_size + self.num_spare_cols):
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self.add_pin(self.data_name + "_{0}".format(i), "INPUT")
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for i in range(self.word_size + self.num_spare_cols):
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT")
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if self.write_size:
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for i in range(self.num_wmasks + self.num_spare_cols):
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self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
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elif self.num_spare_cols and not self.write_size:
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for i in range(self.num_spare_cols + 1):
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self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
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else:
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self.add_pin(self.en_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.driver = factory.create(module_type="write_driver")
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self.add_mod(self.driver)
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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def create_write_array(self):
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self.driver_insts = {}
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w = 0
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windex=0
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for i in range(0, self.columns, self.words_per_row):
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name = "write_driver{}".format(i)
|
||||
index = int(i / self.words_per_row)
|
||||
self.driver_insts[index]=self.add_inst(name=name,
|
||||
mod=self.driver)
|
||||
|
||||
if self.write_size:
|
||||
self.connect_inst([self.data_name + "_{0}".format(index),
|
||||
self.get_bl_name() + "_{0}".format(index),
|
||||
self.get_br_name() + "_{0}".format(index),
|
||||
self.en_name + "_{0}".format(windex), "vdd", "gnd"])
|
||||
w+=1
|
||||
# when w equals write size, the next en pin can be connected since we are now at the next wmask bit
|
||||
if w == self.write_size:
|
||||
w = 0
|
||||
windex+=1
|
||||
|
||||
elif self.num_spare_cols and not self.write_size:
|
||||
self.connect_inst([self.data_name + "_{0}".format(index),
|
||||
self.get_bl_name() + "_{0}".format(index),
|
||||
self.get_br_name() + "_{0}".format(index),
|
||||
self.en_name + "_{0}".format(0), "vdd", "gnd"])
|
||||
|
||||
else:
|
||||
self.connect_inst([self.data_name + "_{0}".format(index),
|
||||
self.get_bl_name() + "_{0}".format(index),
|
||||
self.get_br_name() + "_{0}".format(index),
|
||||
self.en_name, "vdd", "gnd"])
|
||||
|
||||
for i in range(self.num_spare_cols):
|
||||
index = self.word_size + i
|
||||
if self.write_size:
|
||||
offset = self.num_wmasks
|
||||
else:
|
||||
offset = 1
|
||||
name = "write_driver{}".format(self.columns + i)
|
||||
self.driver_insts[index]=self.add_inst(name=name,
|
||||
mod=self.driver)
|
||||
|
||||
self.connect_inst([self.data_name + "_{0}".format(index),
|
||||
self.get_bl_name() + "_{0}".format(index),
|
||||
self.get_br_name() + "_{0}".format(index),
|
||||
self.en_name + "_{0}".format(i + offset), "vdd", "gnd"])
|
||||
|
||||
def place_write_array(self):
|
||||
from tech import cell_properties
|
||||
if self.bitcell.width > self.driver.width:
|
||||
self.driver_spacing = self.bitcell.width
|
||||
else:
|
||||
self.driver_spacing = self.driver.width
|
||||
for i in range(0, self.columns, self.words_per_row):
|
||||
index = int(i / self.words_per_row)
|
||||
xoffset = i * self.driver_spacing
|
||||
|
||||
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
|
||||
mirror = "MY"
|
||||
xoffset = xoffset + self.driver.width
|
||||
else:
|
||||
mirror = ""
|
||||
|
||||
base = vector(xoffset, 0)
|
||||
self.driver_insts[index].place(offset=base, mirror=mirror)
|
||||
|
||||
# place spare write drivers (if spare columns are specified)
|
||||
for i in range(self.num_spare_cols):
|
||||
index = self.word_size + i
|
||||
xoffset = (self.columns + i) * self.driver_spacing
|
||||
|
||||
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
|
||||
mirror = "MY"
|
||||
xoffset = xoffset + self.driver.width
|
||||
else:
|
||||
mirror = ""
|
||||
|
||||
base = vector(xoffset, 0)
|
||||
self.driver_insts[index].place(offset=base, mirror=mirror)
|
||||
|
||||
def add_layout_pins(self):
|
||||
for i in range(self.word_size + self.num_spare_cols):
|
||||
inst = self.driver_insts[i]
|
||||
din_pin = inst.get_pin(inst.mod.din_name)
|
||||
self.add_layout_pin(text=self.data_name + "_{0}".format(i),
|
||||
layer=din_pin.layer,
|
||||
offset=din_pin.ll(),
|
||||
width=din_pin.width(),
|
||||
height=din_pin.height())
|
||||
bl_pin = inst.get_pin(inst.mod.get_bl_names())
|
||||
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll(),
|
||||
width=bl_pin.width(),
|
||||
height=bl_pin.height())
|
||||
|
||||
br_pin = inst.get_pin(inst.mod.get_br_names())
|
||||
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
|
||||
layer=br_pin.layer,
|
||||
offset=br_pin.ll(),
|
||||
width=br_pin.width(),
|
||||
height=br_pin.height())
|
||||
|
||||
for n in ["vdd", "gnd"]:
|
||||
pin_list = self.driver_insts[i].get_pins(n)
|
||||
for pin in pin_list:
|
||||
self.add_power_pin(name=n,
|
||||
loc=pin.center(),
|
||||
directions=("V", "V"),
|
||||
start_layer=pin.layer)
|
||||
if self.write_size:
|
||||
for bit in range(self.num_wmasks):
|
||||
inst = self.driver_insts[bit * self.write_size]
|
||||
en_pin = inst.get_pin(inst.mod.en_name)
|
||||
# Determine width of wmask modified en_pin with/without col mux
|
||||
wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
|
||||
if (self.words_per_row == 1):
|
||||
en_gap = self.driver_spacing - en_pin.width()
|
||||
else:
|
||||
en_gap = self.driver_spacing
|
||||
|
||||
self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
|
||||
layer=en_pin.layer,
|
||||
offset=en_pin.ll(),
|
||||
width=wmask_en_len - en_gap,
|
||||
height=en_pin.height())
|
||||
|
||||
for i in range(self.num_spare_cols):
|
||||
inst = self.driver_insts[self.word_size + i]
|
||||
en_pin = inst.get_pin(inst.mod.en_name)
|
||||
self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks),
|
||||
layer="m1",
|
||||
offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
|
||||
|
||||
elif self.num_spare_cols and not self.write_size:
|
||||
# shorten enable rail to accomodate those for spare write drivers
|
||||
inst = self.driver_insts[0]
|
||||
en_pin = inst.get_pin(inst.mod.en_name)
|
||||
self.add_layout_pin(text=self.en_name + "_{0}".format(0),
|
||||
layer="m1",
|
||||
offset=en_pin.ll(),
|
||||
width=self.width_regular_cols - self.words_per_row * en_pin.width())
|
||||
|
||||
# individual enables for every spare write driver
|
||||
for i in range(self.num_spare_cols):
|
||||
inst = self.driver_insts[self.word_size + i]
|
||||
en_pin = inst.get_pin(inst.mod.en_name)
|
||||
self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1),
|
||||
layer="m1",
|
||||
offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
|
||||
|
||||
else:
|
||||
inst = self.driver_insts[0]
|
||||
self.add_layout_pin(text=self.en_name,
|
||||
layer="m1",
|
||||
offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
|
||||
width=self.width)
|
||||
|
||||
def get_w_en_cin(self):
|
||||
"""Get the relative capacitance of all the enable connections in the bank"""
|
||||
# The enable is connected to a nand2 for every row.
|
||||
return self.driver.get_w_en_cin() * len(self.driver_insts)
|
||||
@@ -0,0 +1,117 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
from bitcell_base_array import bitcell_base_array
|
||||
from tech import drc, spice
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
|
||||
|
||||
class bitcell_array(bitcell_base_array):
|
||||
"""
|
||||
Creates a rows x cols array of memory cells. Assumes bit-lines
|
||||
and word line is connected by abutment.
|
||||
Connects the word lines and bit lines.
|
||||
"""
|
||||
def __init__(self, cols, rows, name, column_offset=0):
|
||||
super().__init__(cols, rows, name, column_offset)
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
# We don't offset this because we need to align
|
||||
# the replica bitcell in the control logic
|
||||
# self.offset_all_coordinates()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.place_array("bit_r{0}_c{1}")
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
self.cell = factory.create(module_type="bitcell")
|
||||
self.add_mod(self.cell)
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
for col in range(self.column_size):
|
||||
for row in range(self.row_size):
|
||||
name = "bit_r{0}_c{1}".format(row, col)
|
||||
self.cell_inst[row, col]=self.add_inst(name=name,
|
||||
mod=self.cell)
|
||||
self.connect_inst(self.get_bitcell_pins(col, row))
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
|
||||
# Dynamic Power from Bitline
|
||||
bl_wire = self.gen_bl_wire()
|
||||
cell_load = 2 * bl_wire.return_input_cap()
|
||||
bl_swing = OPTS.rbl_delay_percentage
|
||||
freq = spice["default_event_frequency"]
|
||||
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
||||
|
||||
# Calculate the bitcell power which currently only includes leakage
|
||||
cell_power = self.cell.analytical_power(corner, load)
|
||||
|
||||
# Leakage power grows with entire array and bitlines.
|
||||
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
||||
cell_power.leakage * self.column_size * self.row_size)
|
||||
return total_power
|
||||
|
||||
def gen_wl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
width = 0
|
||||
else:
|
||||
width = self.width
|
||||
wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_m1"))
|
||||
wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
|
||||
return wl_wire
|
||||
|
||||
def gen_bl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
height = 0
|
||||
else:
|
||||
height = self.height
|
||||
bl_pos = 0
|
||||
bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def get_wordline_cin(self):
|
||||
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
||||
# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
||||
bitcell_wl_cin = self.cell.get_wl_cin()
|
||||
total_cin = bitcell_wl_cin * self.column_size
|
||||
return total_cin
|
||||
|
||||
def graph_exclude_bits(self, targ_row, targ_col):
|
||||
"""Excludes bits in column from being added to graph except target"""
|
||||
# Function is not robust with column mux configurations
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
if row == targ_row and col == targ_col:
|
||||
continue
|
||||
self.graph_inst_exclude.add(self.cell_inst[row, col])
|
||||
|
||||
def get_cell_name(self, inst_name, row, col):
|
||||
"""Gets the spice name of the target bitcell."""
|
||||
return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]
|
||||
@@ -88,7 +88,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
^ dummy columns ^
|
||||
1 x (rows + 4)
|
||||
"""
|
||||
|
||||
# Bitcell array
|
||||
self.bitcell_array = factory.create(module_type="bitcell_array",
|
||||
column_offset=1 + self.add_left_rbl,
|
||||
@@ -109,6 +108,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
||||
replica_bit = self.left_rbl + self.row_size + 1 + bit
|
||||
# If we have an odd numer on the bottom
|
||||
column_offset = self.left_rbl + 1
|
||||
|
||||
self.replica_columns[bit] = factory.create(module_type="replica_column",
|
||||
rows=self.row_size,
|
||||
rbl=self.rbl,
|
||||
|
||||
Reference in New Issue
Block a user