single port progess

compiler/example_configs/run1.py

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+word_size = 2
+num_words = 16
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+#netlist_only = True
+route_supplies = True
+check_lvsdrc = True
+
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run2.py

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+word_size = 8
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run3.py

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+word_size = 16
+num_words = 256
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run4.py

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+word_size = 32
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run5.py

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+word_size = 64
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+output_path = "/home/jesse/thesis/outputs/run5"
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/s8config.py

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+word_size = 16
+num_words = 16
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "sky130"
+
+
+
+accuracy_requirement = 0.05
+magic_exe = ("magic", "magic")
+nominal_corners_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+netlist_only = False
+route_supplies = "grid"
+check_lvsdrc = False
+
+#replica_bitcell_array = "/home/jesse/openram/technology/sky130/modules/replica_bitcell_array.py"
+
+output_path = "sram_" + str(accuracy_requirement)
+output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,
+                                        num_words,
+                                        tech_name,
+                                        accuracy_requirement
+                                        )
+write_size=8