Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

compiler/modules/bitcell.py

@@ -36,8 +36,7 @@ class bitcell(design.design):
         return result
         
     def analytical_power(self, proc, vdd, temp, load):
-        #Power of the bitcell. Mostly known for leakage, but dynamic can also be factored in.
-        #Only consider leakage power for now. Value defined in tech file rather than calculated.
+        """Bitcell power in nW. Only characterizes leakage."""
         from tech import spice
         leakage = spice["bitcell_leakage"]
         dynamic = 0 #temporary

compiler/modules/bitcell_array.py

@@ -179,24 +179,20 @@ class bitcell_array(design.design):
                                  wl_to_cell_delay.slew)
                         
     def analytical_power(self, proc, vdd, temp, load):
-        #This will be pretty bare bones as the power needs to be determined from the dynamic power
-        #of the word line, leakage power from the cell, and dynamic power of the bitlines as a few
-        #sources for power. These features are tbd.
+        """Power of Bitcell array and bitline in nW."""
         from tech import drc
         
-        #calculate wl dynamic power, functions not implemented.
-        
         # Dynamic Power from Bitline
         bl_wire = self.gen_bl_wire()
         cell_load = 2 * bl_wire.return_input_cap() 
-        bl_swing = 0.1 #This should probably be defined in the tech file
+        bl_swing = 0.1 #This should probably be defined in the tech file or input
         freq = spice["default_event_rate"]
         bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
         
-        #Calculate the bitcell power which can include leakage as well as bitline dynamic
+        #Calculate the bitcell power which currently only includes leakage 
         cell_power = self.cell.analytical_power(proc, vdd, temp, load)
         
-        #Leakage power grows with entire array. Dynamic currently not accounted for.
+        #Leakage power grows with entire array and bitlines.
         total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
                                         cell_power.leakage * self.column_size * self.row_size)
         return total_power

compiler/modules/ms_flop.py

@@ -28,17 +28,18 @@ class ms_flop(design.design):
         return result
         
     def analytical_power(self, proc, vdd, temp, load):
-        #Returns dynamic and leakage power. Results in nW
+        """Returns dynamic and leakage power. Results in nW"""
         from tech import spice
         c_eff = self.calculate_effective_capacitance(load)
         f = spice["default_event_rate"]
         power_dyn = c_eff*vdd*vdd*f
-        power_leak = spice["nor2_leakage"]
+        power_leak = spice["msflop_leakage"]
         
         total_power = self.return_power(power_dyn, power_leak)
         return total_power
         
     def calculate_effective_capacitance(self, load):
+        """Computes effective capacitance. Results in fF"""
         from tech import spice, parameter
         c_load = load
         c_para = spice["flop_para_cap"]#ff

compiler/modules/sense_amp.py

@@ -31,6 +31,7 @@ class sense_amp(design.design):
         return self.return_delay(result.delay, result.slew)
 
     def analytical_power(self, proc, vdd, temp, load):
-        #Not sure how to determine this yet. Sense amps return zero power for now
+        """Returns dynamic and leakage power. Results in nW"""
+        #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
         total_power = self.return_power()
         return total_power

compiler/modules/tri_gate.py

@@ -34,11 +34,11 @@ class tri_gate(design.design):
         return self.cal_delay_with_rc(r = r, c =  c_para+load, slew = slew)
         
     def analytical_power(self, proc, vdd, temp, load):
-        #Not sure how to determine this yet. Tri-gates return zero power for now
-        total_power = self.return_power()
+        """Returns dynamic and leakage power. Results in nW"""
+        #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
+        total_power = self.return_power() 
         return total_power
 
-
     def input_load(self):
         return 9*spice["min_tx_gate_c"]