From d0dcd9f34b56b7c659d2034de24c720915f475cd Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 1 Mar 2018 23:34:15 -0800 Subject: [PATCH] Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. --- compiler/modules/bitcell.py | 3 +-- compiler/modules/bitcell_array.py | 12 ++++-------- compiler/modules/ms_flop.py | 5 +++-- compiler/modules/sense_amp.py | 3 ++- compiler/modules/tri_gate.py | 6 +++--- compiler/pgates/pinv.py | 3 ++- compiler/pgates/pnand2.py | 3 ++- compiler/pgates/pnand3.py | 3 ++- compiler/pgates/pnor2.py | 3 ++- technology/scn3me_subm/tech/tech.py | 14 ++++++++++++++ 10 files changed, 35 insertions(+), 20 deletions(-) diff --git a/compiler/modules/bitcell.py b/compiler/modules/bitcell.py index 1fe60867..0cb80635 100644 --- a/compiler/modules/bitcell.py +++ b/compiler/modules/bitcell.py @@ -36,8 +36,7 @@ class bitcell(design.design): return result def analytical_power(self, proc, vdd, temp, load): - #Power of the bitcell. Mostly known for leakage, but dynamic can also be factored in. - #Only consider leakage power for now. Value defined in tech file rather than calculated. + """Bitcell power in nW. Only characterizes leakage.""" from tech import spice leakage = spice["bitcell_leakage"] dynamic = 0 #temporary diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 6224dfae..f923f1f8 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -179,24 +179,20 @@ class bitcell_array(design.design): wl_to_cell_delay.slew) def analytical_power(self, proc, vdd, temp, load): - #This will be pretty bare bones as the power needs to be determined from the dynamic power - #of the word line, leakage power from the cell, and dynamic power of the bitlines as a few - #sources for power. These features are tbd. + """Power of Bitcell array and bitline in nW.""" from tech import drc - #calculate wl dynamic power, functions not implemented. - # Dynamic Power from Bitline bl_wire = self.gen_bl_wire() cell_load = 2 * bl_wire.return_input_cap() - bl_swing = 0.1 #This should probably be defined in the tech file + bl_swing = 0.1 #This should probably be defined in the tech file or input freq = spice["default_event_rate"] bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct - #Calculate the bitcell power which can include leakage as well as bitline dynamic + #Calculate the bitcell power which currently only includes leakage cell_power = self.cell.analytical_power(proc, vdd, temp, load) - #Leakage power grows with entire array. Dynamic currently not accounted for. + #Leakage power grows with entire array and bitlines. total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size, cell_power.leakage * self.column_size * self.row_size) return total_power diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py index 0137ff8b..e04b4246 100644 --- a/compiler/modules/ms_flop.py +++ b/compiler/modules/ms_flop.py @@ -28,17 +28,18 @@ class ms_flop(design.design): return result def analytical_power(self, proc, vdd, temp, load): - #Returns dynamic and leakage power. Results in nW + """Returns dynamic and leakage power. Results in nW""" from tech import spice c_eff = self.calculate_effective_capacitance(load) f = spice["default_event_rate"] power_dyn = c_eff*vdd*vdd*f - power_leak = spice["nor2_leakage"] + power_leak = spice["msflop_leakage"] total_power = self.return_power(power_dyn, power_leak) return total_power def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" from tech import spice, parameter c_load = load c_para = spice["flop_para_cap"]#ff diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index 741c81b1..45a195fc 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -31,6 +31,7 @@ class sense_amp(design.design): return self.return_delay(result.delay, result.slew) def analytical_power(self, proc, vdd, temp, load): - #Not sure how to determine this yet. Sense amps return zero power for now + """Returns dynamic and leakage power. Results in nW""" + #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). total_power = self.return_power() return total_power diff --git a/compiler/modules/tri_gate.py b/compiler/modules/tri_gate.py index 235c0c40..cce7683c 100644 --- a/compiler/modules/tri_gate.py +++ b/compiler/modules/tri_gate.py @@ -34,11 +34,11 @@ class tri_gate(design.design): return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) def analytical_power(self, proc, vdd, temp, load): - #Not sure how to determine this yet. Tri-gates return zero power for now - total_power = self.return_power() + """Returns dynamic and leakage power. Results in nW""" + #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). + total_power = self.return_power() return total_power - def input_load(self): return 9*spice["min_tx_gate_c"] diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 84f14590..7bf71e5d 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -243,7 +243,7 @@ class pinv(pgate.pgate): return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) def analytical_power(self, proc, vdd, temp, load): - #Returns dynamic and leakage power. Results in nW + """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) freq = spice["default_event_rate"] power_dyn = c_eff*vdd*vdd*freq @@ -253,6 +253,7 @@ class pinv(pgate.pgate): return total_power def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transistion_prob = spice["inv_transisition_prob"] diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index c95e814c..fa576850 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -215,7 +215,7 @@ class pnand2(pgate.pgate): return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) def analytical_power(self, proc, vdd, temp, load): - #Returns dynamic and leakage power. Results in nW + """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) freq = spice["default_event_rate"] power_dyn = c_eff*vdd*vdd*freq @@ -225,6 +225,7 @@ class pnand2(pgate.pgate): return total_power def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transistion_prob = spice["nand2_transisition_prob"] diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index ca1c6244..02262b39 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -235,7 +235,7 @@ class pnand3(pgate.pgate): return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) def analytical_power(self, proc, vdd, temp, load): - #Returns dynamic and leakage power. Results in nW + """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) freq = spice["default_event_rate"] power_dyn = c_eff*vdd*vdd*freq @@ -245,6 +245,7 @@ class pnand3(pgate.pgate): return total_power def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transistion_prob = spice["nand3_transisition_prob"] diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 1508a487..4ee1583e 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -225,7 +225,7 @@ class pnor2(pgate.pgate): return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) def analytical_power(self, proc, vdd, temp, load): - #Returns dynamic and leakage power. Results in nW + """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) freq = spice["default_event_rate"] power_dyn = c_eff*vdd*vdd*freq @@ -235,6 +235,7 @@ class pnor2(pgate.pgate): return total_power def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff transistion_prob = spice["nor2_transisition_prob"] diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index fbb4cb7b..faafb7db 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -246,7 +246,21 @@ spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["msflop_leakage"] = 1 # Leakage power of flop in nW +spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transisition_prob"] = .5 # Transition probability of inverter. +spice["inv_transisition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters ###################################################