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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.
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@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
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import tech
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debug.info(2, "Checking min size NMOS with 1 finger")
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fet = ptx.ptx(name="nmos_1_finger",
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width=tech.drc["minwidth_tx"],
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=1,
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tx_type="nmos")
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# return it back to it's normal state
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@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
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import tech
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debug.info(2, "Checking min size PMOS with 1 finger")
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fet = ptx.ptx(name="pmos_1_finger",
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width=tech.drc["minwidth_tx"],
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=1,
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tx_type="pmos")
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# return it back to it's normal state
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@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
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import tech
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debug.info(2, "Checking three fingers NMOS")
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fet = ptx.ptx(name="nmos_3_fingers",
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width=tech.drc["minwidth_tx"],
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=3,
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tx_type="nmos")
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# return it back to it's normal state
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@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
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import tech
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debug.info(2, "Checking three fingers PMOS")
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fet = ptx.ptx(name="pmos_3_fingers",
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width=tech.drc["minwidth_tx"],
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=3,
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tx_type="pmos")
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# return it back to it's normal state
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