diff --git a/compiler/hierarchy_layout.py b/compiler/hierarchy_layout.py
index 36475a72..0251a124 100644
--- a/compiler/hierarchy_layout.py
+++ b/compiler/hierarchy_layout.py
@@ -126,7 +126,7 @@ class layout:
                        offset=offset)
 
 
-    def add_label(self, text, layer, offset=[0,0],zoom=1):
+    def add_label(self, text, layer, offset=[0,0],zoom=0.05):
         """Adds a text label on the given layer,offset, and zoom level"""
         # negative layers indicate "unused" layers in a given technology
         layerNumber = techlayer[layer]
@@ -231,11 +231,10 @@ class layout:
         self.connect_inst([])
         return via
 
-    def add_ptx(self, name, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
+    def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
         """Adds a ptx module to the design."""
         import ptx
-        mos = ptx.ptx(name=name,
-                      width=width,
+        mos = ptx.ptx(width=width,
                       mults=mults,
                       tx_type=tx_type)
         self.add_mod(mos)
diff --git a/compiler/nand_2.py b/compiler/nand_2.py
index 775be9da..4db2324e 100644
--- a/compiler/nand_2.py
+++ b/compiler/nand_2.py
@@ -66,24 +66,20 @@ class nand_2(design.design):
     # transistors are created here but not yet placed or added as a module
     def create_ptx(self):
         """ Add required modules """
-        self.nmos1 = ptx(name="nand_2_nmos1",
-                         width=self.nmos_size,
+        self.nmos1 = ptx(width=self.nmos_size,
                          mults=self.tx_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos1)
-        self.nmos2 = ptx(name="nand_2_nmos2",
-                         width=self.nmos_size,
+        self.nmos2 = ptx(width=self.nmos_size,
                          mults=self.tx_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos2)
 
-        self.pmos1 = ptx(name="nand_2_pmos1",
-                         width=self.pmos_size,
+        self.pmos1 = ptx(width=self.pmos_size,
                          mults=self.tx_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos1)
-        self.pmos2 = ptx(name="nand_2_pmos2",
-                         width=self.pmos_size,
+        self.pmos2 = ptx(width=self.pmos_size,
                          mults=self.tx_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos2)
diff --git a/compiler/nand_3.py b/compiler/nand_3.py
index b8e67f44..2e16d8da 100644
--- a/compiler/nand_3.py
+++ b/compiler/nand_3.py
@@ -65,34 +65,28 @@ class nand_3(design.design):
 
     def create_ptx(self):
         """ Create ptx  but not yet placed"""
-        self.nmos1 = ptx(name="nand_3_nmos1",
-                         width=self.nmos_size,
+        self.nmos1 = ptx(width=self.nmos_size,
                          mults=self.tx_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos1)
-        self.nmos2 = ptx(name="nand_3_nmos2",
-                         width=self.nmos_size,
+        self.nmos2 = ptx(width=self.nmos_size,
                          mults=self.tx_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos2)
-        self.nmos3 = ptx(name="nand_3_nmos3",
-                         width=self.nmos_size,
+        self.nmos3 = ptx(width=self.nmos_size,
                          mults=self.tx_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos3)
 
-        self.pmos1 = ptx(name="nand_3_pmos1",
-                         width=self.pmos_size,
+        self.pmos1 = ptx(width=self.pmos_size,
                          mults=self.tx_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos1)
-        self.pmos2 = ptx(name="nand_3_pmos2",
-                         width=self.pmos_size,
+        self.pmos2 = ptx(width=self.pmos_size,
                          mults=self.tx_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos2)
-        self.pmos3 = ptx(name="nand_3_pmos3",
-                         width=self.pmos_size,
+        self.pmos3 = ptx(width=self.pmos_size,
                          mults=self.tx_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos3)
diff --git a/compiler/nor_2.py b/compiler/nor_2.py
index b2de66fd..59670e68 100644
--- a/compiler/nor_2.py
+++ b/compiler/nor_2.py
@@ -61,12 +61,10 @@ class nor_2(design.design):
         for pmos_mults in range(1, 5):
             nmos_size = self.nmos_width
             pmos_size = 4 * self.nmos_width / pmos_mults
-            test_nmos = ptx(name="testp",
-                            width=nmos_size,
+            test_nmos = ptx(width=nmos_size,
                             mults=nmos_mults,
                             tx_type="nmos")
-            test_pmos = ptx(name="testn",
-                            width=pmos_size,
+            test_pmos = ptx(width=pmos_size,
                             mults=pmos_mults,
                             tx_type="nmos")
             
@@ -96,24 +94,20 @@ class nor_2(design.design):
 
     def create_modules(self):
         """transistors are created as modules"""
-        self.nmos1 = ptx(name="nor_2_nmos1",
-                         width=self.nmos_size,
+        self.nmos1 = ptx(width=self.nmos_size,
                          mults=self.nmos_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos1)
-        self.nmos2 = ptx(name="nor_2_nmos2",
-                         width=self.nmos_size,
+        self.nmos2 = ptx(width=self.nmos_size,
                          mults=self.nmos_mults,
                          tx_type="nmos")
         self.add_mod(self.nmos2)
 
-        self.pmos1 = ptx(name="nor_2_pmos1",
-                         width=self.pmos_size,
+        self.pmos1 = ptx(width=self.pmos_size,
                          mults=self.pmos_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos1)
-        self.pmos2 = ptx(name="nor_2_pmos2",
-                         width=self.pmos_size,
+        self.pmos2 = ptx(width=self.pmos_size,
                          mults=self.pmos_mults,
                          tx_type="pmos")
         self.add_mod(self.pmos2)
diff --git a/compiler/pinv.py b/compiler/pinv.py
index e03f4c06..03575f4b 100644
--- a/compiler/pinv.py
+++ b/compiler/pinv.py
@@ -90,15 +90,13 @@ class pinv(design.design):
 
     def create_ptx(self):
         """Intiializes a ptx object"""
-        self.nmos = ptx(name="inv_nmos1",
-                        width=self.nmos_size,
+        self.nmos = ptx(width=self.nmos_size,
                         mults=self.tx_mults,
                         tx_type="nmos")
         self.nmos.connect_fingered_poly()
         self.nmos.connect_fingered_active()
         self.add_mod(self.nmos)
-        self.pmos = ptx(name="inv_pmos1",
-                        width=self.pmos_size,
+        self.pmos = ptx(width=self.pmos_size,
                         mults=self.tx_mults,
                         tx_type="pmos")
         self.pmos.connect_fingered_poly()
diff --git a/compiler/precharge.py b/compiler/precharge.py
index c5eb6a31..e64370b6 100644
--- a/compiler/precharge.py
+++ b/compiler/precharge.py
@@ -45,19 +45,16 @@ class precharge(design.design):
 
     def create_ptx(self):
         """Initializes the upper and lower pmos"""
-        self.lower_pmos = ptx(name="lower_pmos", 
-                              width=self.ptx_width, 
+        self.lower_pmos = ptx(width=self.ptx_width,
                               mults=1, 
                               tx_type="pmos")
         self.add_mod(self.lower_pmos)
-        self.upper_pmos = ptx(name="upper_pmos",
-                              width=self.beta * self.ptx_width,
+        self.upper_pmos = ptx(width=self.beta * self.ptx_width,
                               mults=1,
                               tx_type="pmos")
         self.upper_pmos = self.upper_pmos
         self.add_mod(self.upper_pmos)
-        self.temp_pmos = ptx(name="temp_upper_pmos",
-                             width=self.beta * self.ptx_width,
+        self.temp_pmos = ptx(width=self.beta * self.ptx_width,
                              mults=2,
                              tx_type="pmos")
         self.temp_pmos.remove_source_connect()
diff --git a/compiler/ptx.py b/compiler/ptx.py
index 0821f762..a14c4e56 100644
--- a/compiler/ptx.py
+++ b/compiler/ptx.py
@@ -9,12 +9,8 @@ class ptx(design.design):
     This module generates gds and spice of a parametrically NMOS or PMOS sized transistor. 
     Creates a simple MOS transistor
     """
-    # This is used to create a unique MOS ID name by avoiding collisions
-    unique_mos_id = 1
-
-    def __init__(self, name, width=1, mults=1, tx_type="nmos"):
-        name = "{0}{1}".format(name, ptx.unique_mos_id)
-        ptx.unique_mos_id += 1
+    def __init__(self, width=1, mults=1, tx_type="nmos"):
+        name = "{0}_m{1}_w{2}".format(tx_type, mults, width)
         design.design.__init__(self, name)
         debug.info(3, "create ptx structure {0}".format(name))
 
@@ -281,6 +277,8 @@ class ptx(design.design):
             del self.insts[self.drain_connect_index]
             del self.drain_connect_index
             self.offset_all_coordinates()
+            # change the name so it is unique
+            self.name = self.name + "_rd"
         except:
             pass
 
@@ -292,6 +290,8 @@ class ptx(design.design):
             if isinstance(self.drain_connect_index, int):
                 self.drain_connect_index -= 1
             self.offset_all_coordinates()
+            # change the name so it is unique
+            self.name = self.name + "_rs"
         except:
             pass
 
@@ -300,5 +300,7 @@ class ptx(design.design):
         try:
             del self.objs[self.poly_connect_index]
             self.offset_all_coordinates()
+            # change the name so it is unique
+            self.name = self.name + "_rp"
         except:
             pass
diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py
index 6d562937..04154444 100644
--- a/compiler/replica_bitline.py
+++ b/compiler/replica_bitline.py
@@ -109,8 +109,7 @@ class replica_bitline(design.design):
                          nmos_width=drc["minwidth_tx"])
         self.add_mod(self.nor)
 
-        self.access_tx = ptx(name="access_tx",
-                             width=drc["minwidth_tx"],
+        self.access_tx = ptx(width=drc["minwidth_tx"],
                              mults=1,
                              tx_type="pmos")
         self.add_mod(self.access_tx)
diff --git a/compiler/single_level_column_mux.py b/compiler/single_level_column_mux.py
index ab38ceb4..1060e54c 100644
--- a/compiler/single_level_column_mux.py
+++ b/compiler/single_level_column_mux.py
@@ -44,13 +44,11 @@ class single_level_column_mux(design.design):
 
     def create_ptx(self):
         """Initializes the nmos1 and nmos2 transistors"""
-        self.nmos1 = ptx(name="nmos1",
-                         width=self.ptx_width,
+        self.nmos1 = ptx(width=self.ptx_width,
                          mults=1,
                          tx_type="nmos")
         self.add_mod(self.nmos1)
-        self.nmos2 = ptx(name="nmos2",
-                         width=self.ptx_width,
+        self.nmos2 = ptx(width=self.ptx_width,
                          mults=1,
                          tx_type="nmos")
         self.nmos2 = self.nmos2        
diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py
index 3f023020..36719511 100644
--- a/compiler/tests/03_ptx_1finger_nmos_test.py
+++ b/compiler/tests/03_ptx_1finger_nmos_test.py
@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
         import tech
 
         debug.info(2, "Checking min size NMOS with 1 finger")
-        fet = ptx.ptx(name="nmos_1_finger",
-                      width=tech.drc["minwidth_tx"],
+        fet = ptx.ptx(width=tech.drc["minwidth_tx"],
                       mults=1,
                       tx_type="nmos")
         # return it back to it's normal state
diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py
index 4bb3e312..5f5f0897 100644
--- a/compiler/tests/03_ptx_1finger_pmos_test.py
+++ b/compiler/tests/03_ptx_1finger_pmos_test.py
@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
         import tech
 
         debug.info(2, "Checking min size PMOS with 1 finger")
-        fet = ptx.ptx(name="pmos_1_finger",
-                      width=tech.drc["minwidth_tx"],
+        fet = ptx.ptx(width=tech.drc["minwidth_tx"],
                       mults=1,
                       tx_type="pmos")
         # return it back to it's normal state
diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py
index 17ec9092..444ef331 100644
--- a/compiler/tests/03_ptx_3finger_nmos_test.py
+++ b/compiler/tests/03_ptx_3finger_nmos_test.py
@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
         import tech
 
         debug.info(2, "Checking three fingers NMOS")
-        fet = ptx.ptx(name="nmos_3_fingers",
-                      width=tech.drc["minwidth_tx"],
+        fet = ptx.ptx(width=tech.drc["minwidth_tx"],
                       mults=3,
                       tx_type="nmos")
         # return it back to it's normal state
diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py
index f889527d..8f6e6c7b 100644
--- a/compiler/tests/03_ptx_3finger_pmos_test.py
+++ b/compiler/tests/03_ptx_3finger_pmos_test.py
@@ -25,8 +25,7 @@ class ptx_test(unittest.TestCase):
         import tech
 
         debug.info(2, "Checking three fingers PMOS")
-        fet = ptx.ptx(name="pmos_3_fingers",
-                      width=tech.drc["minwidth_tx"],
+        fet = ptx.ptx(width=tech.drc["minwidth_tx"],
                       mults=3,
                       tx_type="pmos")
         # return it back to it's normal state