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start of pattern refactor

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This commit is contained in:
Jesse Cirimelli-Low
2023-07-24 23:25:35 -07:00
parent 7bd312faff
commit cb21443e2d
4 changed files with 191 additions and 40 deletions
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compiler/modules/bitcell_array.py
+25 -14
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@@ -10,7 +10,8 @@ from openram.tech import drc, spice
from openram.sram_factory import factory
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
from .pattern import pattern
from openram.base import geometry, instance
class bitcell_array(bitcell_base_array):
"""
@@ -42,7 +43,7 @@ class bitcell_array(bitcell_base_array):
def create_layout(self):
self.place_array("bit_r{0}_c{1}")
self.place_array()
self.add_layout_pins()
@@ -56,19 +57,29 @@ class bitcell_array(bitcell_base_array):
""" Add the modules used in this design """
self.cell = factory.create(module_type=OPTS.bitcell)
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.cell)
self.connect_inst(self.get_bitcell_pins(row, col))
# def create_instances(self):
# """ Create the module instances used in this design """
# self.cell_inst = {}
# for col in range(self.column_size):
# for row in range(self.row_size):
# name = "bit_r{0}_c{1}".format(row, col)
# self.cell_inst[row, col]=self.add_inst(name=name,
# mod=self.cell)
# self.connect_inst(self.get_bitcell_pins(row, col))
#
# # If it is a "core" cell, it could be trimmed for sim time
# if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
# self.trim_insts.add(name)
# If it is a "core" cell, it could be trimmed for sim time
if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
self.trim_insts.add(name)
def create_instances(self):
self.cell_inst={}
core_block = [[0 for x in range(2)] for y in range(2)]
core_block[0][0] = geometry.instance("core_0_0", mod=self.cell)
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, mirror="MX")
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, mirror="MY")
core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, mirror="XY")
self.pattern = pattern(self, "bitcell_array", core_block, self.row_size/2, self.column_size/2)
def analytical_power(self, corner, load):
"""Power of Bitcell array and bitline in nW."""