Default bitcell opt1

2026-09-07 11:21:14 +02:00 · 2020-10-12 17:08:32 -07:00
parent fecf3b2009
commit ca2ce8b070
3 changed files with 4 additions and 6 deletions
@@ -527,12 +527,10 @@ class simulation():
        """
        Gets the signal name associated with the bitlines in the bank.
        """
-        
        cell_mod = factory.create(module_type=OPTS.bitcell)
        cell_bl = cell_mod.get_bl_name(port)
        cell_br = cell_mod.get_br_name(port)
-        
-        # Only a single path should contain a single s_en name. Anything else is an error.
+            
        bl_names = []
        exclude_set = self.get_bl_name_search_exclusions()
        for int_net in [cell_bl, cell_br]: