diff --git a/compiler/tests/04_column_mux_pbitcell_test.py b/compiler/tests/04_column_mux_pbitcell_test.py index e8d5038b..177f1eba 100755 --- a/compiler/tests/04_column_mux_pbitcell_test.py +++ b/compiler/tests/04_column_mux_pbitcell_test.py @@ -28,12 +28,10 @@ class column_mux_pbitcell_test(openram_test): OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - factory.reset() debug.info(2, "Checking column mux for pbitcell (innermost connections)") tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) - factory.reset() debug.info(2, "Checking column mux for pbitcell (outermost connections)") tx = factory.create(module_type="column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index 9043dbc6..981270ed 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -28,7 +28,6 @@ class replica_pbitcell_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Checking dummy bitcell using pbitcell (small cell)") tx = dummy_pbitcell(name="rpbc") self.local_check(tx) @@ -37,7 +36,6 @@ class replica_pbitcell_test(openram_test): OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - factory.reset() debug.info(2, "Checking dummy bitcell using pbitcell (large cell)") tx = dummy_pbitcell(name="rpbc") self.local_check(tx) diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index d1ab4168..c0338015 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -26,7 +26,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=1 OPTS.num_w_ports=1 OPTS.num_r_ports=1 - factory.reset() debug.info(2, "Bitcell with 1 of each port: read/write, write, and read") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -34,7 +33,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=0 OPTS.num_w_ports=1 OPTS.num_r_ports=1 - factory.reset() debug.info(2, "Bitcell with 0 read/write ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -42,7 +40,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=1 OPTS.num_w_ports=0 OPTS.num_r_ports=1 - factory.reset() debug.info(2, "Bitcell with 0 write ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -50,7 +47,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=1 OPTS.num_w_ports=1 OPTS.num_r_ports=0 - factory.reset() debug.info(2, "Bitcell with 0 read ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -58,7 +54,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=1 OPTS.num_w_ports=0 OPTS.num_r_ports=0 - factory.reset() debug.info(2, "Bitcell with 0 read ports and 0 write ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -66,7 +61,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=2 OPTS.num_w_ports=2 OPTS.num_r_ports=2 - factory.reset() debug.info(2, "Bitcell with 2 of each port: read/write, write, and read") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -74,7 +68,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=0 OPTS.num_w_ports=2 OPTS.num_r_ports=2 - factory.reset() debug.info(2, "Bitcell with 0 read/write ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -82,7 +75,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=2 OPTS.num_w_ports=0 OPTS.num_r_ports=2 - factory.reset() debug.info(2, "Bitcell with 0 write ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -90,7 +82,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=2 OPTS.num_w_ports=2 OPTS.num_r_ports=0 - factory.reset() debug.info(2, "Bitcell with 0 read ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) @@ -98,7 +89,6 @@ class pbitcell_test(openram_test): OPTS.num_rw_ports=2 OPTS.num_w_ports=0 OPTS.num_r_ports=0 - factory.reset() debug.info(2, "Bitcell with 0 read ports and 0 write ports") tx = factory.create(module_type="pbitcell") self.local_check(tx) diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py index 59f01a73..9b422ca5 100755 --- a/compiler/tests/04_precharge_1rw_1r_test.py +++ b/compiler/tests/04_precharge_1rw_1r_test.py @@ -32,7 +32,6 @@ class precharge_test(openram_test): tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) - factory.reset() debug.info(2, "Checking precharge for 1rw1r port 1") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py index 4a228b6e..71024200 100755 --- a/compiler/tests/04_precharge_pbitcell_test.py +++ b/compiler/tests/04_precharge_pbitcell_test.py @@ -28,17 +28,14 @@ class precharge_pbitcell_test(openram_test): OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) - factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) - factory.reset() debug.info(2, "Checking precharge for pbitcell (outermost connections)") tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 00252a84..73d94039 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -28,7 +28,6 @@ class replica_pbitcell_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (small cell)") tx = replica_pbitcell(name="rpbc") self.local_check(tx) @@ -37,7 +36,6 @@ class replica_pbitcell_test(openram_test): OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - factory.reset() debug.info(2, "Checking replica bitcell using pbitcell (large cell)") tx = replica_pbitcell(name="rpbc") self.local_check(tx) diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py index 3b731b31..e77922f6 100755 --- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py +++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py @@ -27,17 +27,14 @@ class hierarchical_decoder_pbitcell_test(openram_test): OPTS.num_r_ports = 0 openram.setup_bitcell() - factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=16) self.local_check(a) - factory.reset() debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=17) self.local_check(a) - factory.reset() debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=23) self.local_check(a) @@ -46,7 +43,6 @@ class hierarchical_decoder_pbitcell_test(openram_test): a = factory.create(module_type="hierarchical_decoder", num_outputs=32) self.local_check(a) - factory.reset() debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=65) self.local_check(a) @@ -55,7 +51,6 @@ class hierarchical_decoder_pbitcell_test(openram_test): a = factory.create(module_type="hierarchical_decoder", num_outputs=128) self.local_check(a) - factory.reset() debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)") a = factory.create(module_type="hierarchical_decoder", num_outputs=341) self.local_check(a) diff --git a/compiler/tests/07_column_mux_array_pbitcell_test.py b/compiler/tests/07_column_mux_array_pbitcell_test.py index 020696fa..9f082218 100755 --- a/compiler/tests/07_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_column_mux_array_pbitcell_test.py @@ -27,7 +27,6 @@ class column_mux_pbitcell_test(openram_test): OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - factory.reset() debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") a = factory.create(module_type="column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py index e9b2bce4..739d8006 100755 --- a/compiler/tests/08_precharge_array_1rw_1r_test.py +++ b/compiler/tests/08_precharge_array_1rw_1r_test.py @@ -28,7 +28,6 @@ class precharge_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - factory.reset() debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)") pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) diff --git a/compiler/tests/08_wordline_driver_array_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py index 5162bf1f..9eb3bdfd 100755 --- a/compiler/tests/08_wordline_driver_array_pbitcell_test.py +++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py @@ -28,7 +28,6 @@ class wordline_driver_array_pbitcell_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Checking driver (multi-port case)") tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64) self.local_check(tx) diff --git a/compiler/tests/09_sense_amp_array_pbitcell_test.py b/compiler/tests/09_sense_amp_array_pbitcell_test.py index ae1186b7..2040b4b2 100755 --- a/compiler/tests/09_sense_amp_array_pbitcell_test.py +++ b/compiler/tests/09_sense_amp_array_pbitcell_test.py @@ -28,7 +28,6 @@ class sense_amp_pbitcell_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) self.local_check(a) diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py index c39fd094..981cc6ae 100755 --- a/compiler/tests/09_sense_amp_array_spare_cols_test.py +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -37,7 +37,6 @@ class sense_amp_array_spare_cols_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2, num_spare_cols=2 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2, num_spare_cols=2) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py index 1a72989b..e5914935 100755 --- a/compiler/tests/10_write_driver_array_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_pbitcell_test.py @@ -28,7 +28,6 @@ class write_driver_pbitcell_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") a = factory.create(module_type="write_driver_array", columns=8, word_size=8) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py index ef0c3596..a1926a90 100755 --- a/compiler/tests/10_write_driver_array_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -37,7 +37,6 @@ class write_driver_array_spare_cols_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py index 69054586..7bc6704d 100755 --- a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py +++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py @@ -28,7 +28,6 @@ class write_driver_pbitcell_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)") a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4) self.local_check(a) diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py index 3d79d4dd..e19bfd27 100755 --- a/compiler/tests/10_write_mask_and_array_pbitcell_test.py +++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py @@ -28,7 +28,6 @@ class write_mask_and_array_pbitcell_test(openram_test): OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - factory.reset() debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)") a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py index b4ba91d1..61464b9b 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py @@ -24,7 +24,6 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Testing 4x4 array for bitcell") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py index 175689c3..070404ac 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -24,7 +24,6 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Testing 4x4 array for bitcell") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py index f77a571d..b8d5e5ed 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py @@ -24,7 +24,6 @@ class replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Testing 4x4 array for bitcell") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py index e893c3ca..219bd680 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py @@ -24,7 +24,6 @@ class replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Testing 4x4 array for bitcell") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py index cb143c40..a7d0f077 100755 --- a/compiler/tests/14_replica_pbitcell_array_test.py +++ b/compiler/tests/14_replica_pbitcell_array_test.py @@ -38,7 +38,6 @@ class replica_pbitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() debug.info(2, "Testing 4x4 array for pbitcell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py index 57947481..b4b50323 100755 --- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py @@ -32,7 +32,6 @@ class port_data_1rw_1r_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=16 - factory.reset() c.recompute_sizes() debug.info(1, "Sixteen way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py index 0b1859e4..66d4c4bf 100755 --- a/compiler/tests/18_port_data_16mux_test.py +++ b/compiler/tests/18_port_data_16mux_test.py @@ -36,7 +36,6 @@ class port_data_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=16 - factory.reset() c.recompute_sizes() debug.info(1, "Sixteen way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py index d9ca31ea..fc0d9243 100755 --- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py @@ -31,7 +31,6 @@ class port_data_1rw_1r_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py index 469d3e34..8eb29615 100755 --- a/compiler/tests/18_port_data_2mux_test.py +++ b/compiler/tests/18_port_data_2mux_test.py @@ -35,7 +35,6 @@ class port_data_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py index edd2336b..ac81e561 100755 --- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py @@ -31,7 +31,6 @@ class port_data_1rw_1r_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py index 12ef31d2..c3eae434 100755 --- a/compiler/tests/18_port_data_4mux_test.py +++ b/compiler/tests/18_port_data_4mux_test.py @@ -35,7 +35,6 @@ class port_data_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py index 683a086f..e57d12ef 100755 --- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py @@ -32,7 +32,6 @@ class port_data_1rw_1r_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py index ae067163..a8f82489 100755 --- a/compiler/tests/18_port_data_8mux_test.py +++ b/compiler/tests/18_port_data_8mux_test.py @@ -36,7 +36,6 @@ class port_data_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py index 04cbddd8..8b887d9b 100755 --- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py +++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py @@ -30,7 +30,6 @@ class port_data_1rw_1r_test(openram_test): num_words=16) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py index 07836e3d..e479de1f 100755 --- a/compiler/tests/18_port_data_nomux_test.py +++ b/compiler/tests/18_port_data_nomux_test.py @@ -34,7 +34,6 @@ class port_data_test(openram_test): num_spare_rows=num_spare_rows) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index c511dc5c..0db34da0 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -26,7 +26,6 @@ class port_data_spare_cols_test(openram_test): num_spare_cols=3) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -34,7 +33,6 @@ class port_data_spare_cols_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -43,7 +41,6 @@ class port_data_spare_cols_test(openram_test): c.num_words=64 c.words_per_row=4 c.num_spare_cols=3 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -53,7 +50,6 @@ class port_data_spare_cols_test(openram_test): c.num_words=128 c.words_per_row=8 c.num_spare_cols=4 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -66,7 +62,6 @@ class port_data_spare_cols_test(openram_test): c.num_words=16 c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -76,7 +71,6 @@ class port_data_spare_cols_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -86,7 +80,6 @@ class port_data_spare_cols_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -97,7 +90,6 @@ class port_data_spare_cols_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py index ee3278d2..b731a1d0 100755 --- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py +++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py @@ -31,7 +31,6 @@ class port_data_wmask_1rw_1r_test(openram_test): num_words=16) c.words_per_row = 1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -39,7 +38,6 @@ class port_data_wmask_1rw_1r_test(openram_test): c.num_words = 32 c.words_per_row = 2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -47,7 +45,6 @@ class port_data_wmask_1rw_1r_test(openram_test): c.num_words = 64 c.words_per_row = 4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -55,7 +52,6 @@ class port_data_wmask_1rw_1r_test(openram_test): c.num_words = 128 c.words_per_row = 8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -68,7 +64,6 @@ class port_data_wmask_1rw_1r_test(openram_test): c.num_words = 16 c.words_per_row = 1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -78,7 +73,6 @@ class port_data_wmask_1rw_1r_test(openram_test): # c.num_words = 32 c.words_per_row = 2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -88,7 +82,6 @@ class port_data_wmask_1rw_1r_test(openram_test): c.num_words = 64 c.words_per_row = 4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -99,7 +92,6 @@ class port_data_wmask_1rw_1r_test(openram_test): c.word_size = 8 c.num_words = 128 c.words_per_row = 8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index e1860e6e..3db910c1 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -35,7 +35,6 @@ class port_data_wmask_test(openram_test): num_spare_rows=num_spare_rows) c.words_per_row = 1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -43,7 +42,6 @@ class port_data_wmask_test(openram_test): c.num_words = 32 c.words_per_row = 2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -51,7 +49,6 @@ class port_data_wmask_test(openram_test): c.num_words = 64 c.words_per_row = 4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -59,7 +56,6 @@ class port_data_wmask_test(openram_test): c.num_words = 128 c.words_per_row = 8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -72,7 +68,6 @@ class port_data_wmask_test(openram_test): c.num_words = 16 c.words_per_row = 1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -82,7 +77,6 @@ class port_data_wmask_test(openram_test): # c.num_words = 32 c.words_per_row = 2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -92,7 +86,6 @@ class port_data_wmask_test(openram_test): c.num_words = 64 c.words_per_row = 4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("port_data", sram_config=c, port=0) @@ -103,7 +96,6 @@ class port_data_wmask_test(openram_test): c.word_size = 8 c.num_words = 128 c.words_per_row = 8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("port_data", sram_config=c, port=0) diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index a1fb9b57..c1f408e0 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -29,7 +29,6 @@ class multi_bank_test(openram_test): c.num_banks=2 c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) @@ -37,7 +36,6 @@ class multi_bank_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) @@ -45,7 +43,6 @@ class multi_bank_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) @@ -54,7 +51,6 @@ class multi_bank_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 4e39a32c..378ff837 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -34,7 +34,6 @@ class multi_bank_test(openram_test): c.num_banks=2 c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) @@ -42,7 +41,6 @@ class multi_bank_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) @@ -50,7 +48,6 @@ class multi_bank_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) @@ -59,7 +56,6 @@ class multi_bank_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 205b6bff..cf38b68b 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -36,7 +36,6 @@ class psingle_bank_test(openram_test): num_words=16) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create(module_type="bank", sram_config=c) @@ -44,7 +43,6 @@ class psingle_bank_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create(module_type="bank", sram_config=c) @@ -52,7 +50,6 @@ class psingle_bank_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) @@ -61,7 +58,6 @@ class psingle_bank_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py index 9ce9ee22..4d31ea38 100755 --- a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py @@ -32,7 +32,6 @@ class single_bank_1rw_1r_test(openram_test): num_words=128) c.words_per_row=16 - factory.reset() c.recompute_sizes() debug.info(1, "Sixteen way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_16mux_test.py b/compiler/tests/19_single_bank_16mux_test.py index 889d6e95..2bc53ace 100755 --- a/compiler/tests/19_single_bank_16mux_test.py +++ b/compiler/tests/19_single_bank_16mux_test.py @@ -38,7 +38,6 @@ class single_bank_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=16 - factory.reset() c.recompute_sizes() debug.info(1, "Sixteen way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index ed3594e6..428f6dc6 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -32,7 +32,6 @@ class single_bank_1w_1r_test(openram_test): num_words=16) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create(module_type="bank", sram_config=c) @@ -40,7 +39,6 @@ class single_bank_1w_1r_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create(module_type="bank", sram_config=c) @@ -48,7 +46,6 @@ class single_bank_1w_1r_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) @@ -57,7 +54,6 @@ class single_bank_1w_1r_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py index 14400ece..e81d1bbc 100755 --- a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py @@ -33,7 +33,6 @@ class single_bank_1rw_1r_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_2mux_test.py b/compiler/tests/19_single_bank_2mux_test.py index 897ad100..a1679f5c 100755 --- a/compiler/tests/19_single_bank_2mux_test.py +++ b/compiler/tests/19_single_bank_2mux_test.py @@ -28,7 +28,6 @@ class single_bank_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py index 588055ec..0c1f3439 100755 --- a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py @@ -33,7 +33,6 @@ class single_bank_1rw_1r_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_4mux_test.py b/compiler/tests/19_single_bank_4mux_test.py index def5a5bc..94219f97 100755 --- a/compiler/tests/19_single_bank_4mux_test.py +++ b/compiler/tests/19_single_bank_4mux_test.py @@ -28,7 +28,6 @@ class single_bank_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py index 7e1c9bb4..2a12397c 100755 --- a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py @@ -34,7 +34,6 @@ class single_bank_1rw_1r_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_8mux_test.py b/compiler/tests/19_single_bank_8mux_test.py index 626746b2..bee204a5 100755 --- a/compiler/tests/19_single_bank_8mux_test.py +++ b/compiler/tests/19_single_bank_8mux_test.py @@ -38,7 +38,6 @@ class single_bank_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_global_bitline_test.py b/compiler/tests/19_single_bank_global_bitline_test.py index 5501e485..3649dea4 100755 --- a/compiler/tests/19_single_bank_global_bitline_test.py +++ b/compiler/tests/19_single_bank_global_bitline_test.py @@ -33,7 +33,6 @@ class single_bank_1rw_1r_test(openram_test): num_words=16) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create(module_type="bank", sram_config=c) @@ -41,7 +40,6 @@ class single_bank_1rw_1r_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create(module_type="bank", sram_config=c) @@ -49,7 +47,6 @@ class single_bank_1rw_1r_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create(module_type="bank", sram_config=c) @@ -58,7 +55,6 @@ class single_bank_1rw_1r_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py index 3926df30..14c998ae 100755 --- a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py @@ -32,7 +32,6 @@ class single_bank_1rw_1r_test(openram_test): num_words=16) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create(module_type="bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_nomux_test.py b/compiler/tests/19_single_bank_nomux_test.py index 3c49f975..f7c9b72d 100755 --- a/compiler/tests/19_single_bank_nomux_test.py +++ b/compiler/tests/19_single_bank_nomux_test.py @@ -36,7 +36,6 @@ class single_bank_test(openram_test): num_spare_rows=num_spare_rows) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index 68b71b51..1e3280de 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -28,7 +28,6 @@ class single_bank_spare_cols_test(openram_test): num_spare_cols=3) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) @@ -36,7 +35,6 @@ class single_bank_spare_cols_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) @@ -44,7 +42,6 @@ class single_bank_spare_cols_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) @@ -53,7 +50,6 @@ class single_bank_spare_cols_test(openram_test): c.word_size=2 c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py index 8d810d91..20410bc8 100755 --- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py @@ -34,7 +34,6 @@ class single_bank_wmask_1rw_1r_test(openram_test): num_banks=1) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) @@ -42,7 +41,6 @@ class single_bank_wmask_1rw_1r_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) @@ -50,7 +48,6 @@ class single_bank_wmask_1rw_1r_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) @@ -58,7 +55,6 @@ class single_bank_wmask_1rw_1r_test(openram_test): c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 19b01e61..16a14c6f 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -29,7 +29,6 @@ class single_bank_wmask_test(openram_test): num_banks=1) c.words_per_row=1 - factory.reset() c.recompute_sizes() debug.info(1, "No column mux") a = factory.create("bank", sram_config=c) @@ -37,7 +36,6 @@ class single_bank_wmask_test(openram_test): c.num_words=32 c.words_per_row=2 - factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") a = factory.create("bank", sram_config=c) @@ -45,7 +43,6 @@ class single_bank_wmask_test(openram_test): c.num_words=64 c.words_per_row=4 - factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") a = factory.create("bank", sram_config=c) @@ -53,7 +50,6 @@ class single_bank_wmask_test(openram_test): c.num_words=128 c.words_per_row=8 - factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") a = factory.create("bank", sram_config=c) diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index c2d2c412..52031166 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -38,7 +38,6 @@ class sram_2bank_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) @@ -54,7 +53,6 @@ class sram_2bank_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) @@ -70,7 +68,6 @@ class sram_2bank_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) @@ -87,7 +84,6 @@ class sram_2bank_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True)