diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 63224033..c748e83d 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -393,7 +393,7 @@ class replica_bitcell_array(design.design): # Dynamic Power from Bitline bl_wire = self.gen_bl_wire() cell_load = 2 * bl_wire.return_input_cap() - bl_swing = parameter["rbl_height_percentage"] + bl_swing = OPTS.rbl_delay_percentage freq = spice["default_event_rate"] bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing) @@ -451,4 +451,4 @@ class replica_bitcell_array(design.design): def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" - return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col) \ No newline at end of file + return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index e6ea5a32..9a72edee 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -61,28 +61,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2121267], - 'delay_lh': [0.2121267], - 'leakage_power': 0.0023761999999999998, - 'min_period': 0.43, - 'read0_power': [0.5139368], - 'read1_power': [0.48940979999999995], - 'slew_hl': [0.0516745], - 'slew_lh': [0.0516745], - 'write0_power': [0.46267169999999996], - 'write1_power': [0.4670826]} + golden_data = {'delay_hl': [0.2192123], + 'delay_lh': [0.2192123], + 'leakage_power': 0.006427800000000001, + 'min_period': 0.527, + 'read0_power': [0.4519997], + 'read1_power': [0.42609269999999994], + 'slew_hl': [0.10185999999999999], + 'slew_lh': [0.10185999999999999], + 'write0_power': [0.49744869999999997], + 'write1_power': [0.4460337]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.288], - 'delay_lh': [1.288], - 'leakage_power': 0.0273896, - 'min_period': 2.578, - 'read0_power': [16.9996], - 'read1_power': [16.2616], - 'slew_hl': [0.47891700000000004], - 'slew_lh': [0.47891700000000004], - 'write0_power': [16.0656], - 'write1_power': [16.2616]} - + golden_data = {'delay_hl': [1.4249], + 'delay_lh': [1.4249], + 'leakage_power': 0.7340832, + 'min_period': 3.125, + 'read0_power': [14.8099], + 'read1_power': [14.0866], + 'slew_hl': [0.7280485], + 'slew_lh': [0.7280485], + 'write0_power': [16.865], + 'write1_power': [14.8288]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index a775c086..51edb48f 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -15,8 +15,9 @@ from globals import OPTS from sram_factory import factory import debug -class model_delay_sram_test(openram_test): - +class model_delay_test(openram_test): + """ Compare the accuracy of the analytical model with a spice simulation. """ + def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False @@ -61,9 +62,9 @@ class model_delay_sram_test(openram_test): debug.info(1,"Spice Delays={}".format(spice_delays)) debug.info(1,"Model Delays={}".format(model_delays)) if OPTS.tech_name == "freepdk45": - error_tolerance = .25 + error_tolerance = 0.25 elif OPTS.tech_name == "scn4m_subm": - error_tolerance = .25 + error_tolerance = 0.25 else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 1ff14250..e57ad120 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -54,28 +54,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2108836], - 'delay_lh': [0.2108836], - 'leakage_power': 0.001564799, - 'min_period': 0.508, - 'read0_power': [0.43916689999999997], - 'read1_power': [0.4198608], - 'slew_hl': [0.0455126], - 'slew_lh': [0.0455126], - 'write0_power': [0.40681890000000004], - 'write1_power': [0.4198608]} + golden_data = {'delay_hl': [0.2265453], + 'delay_lh': [0.2265453], + 'leakage_power': 0.003688569, + 'min_period': 0.547, + 'read0_power': [0.4418831], + 'read1_power': [0.41914969999999996], + 'slew_hl': [0.103665], + 'slew_lh': [0.103665], + 'write0_power': [0.48889660000000007], + 'write1_power': [0.4419755]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.5747600000000002], - 'delay_lh': [1.5747600000000002], - 'leakage_power': 0.00195795, - 'min_period': 3.281, - 'read0_power': [14.92874], - 'read1_power': [14.369810000000001], - 'slew_hl': [0.49631959999999997], - 'slew_lh': [0.49631959999999997], - 'write0_power': [13.79953], - 'write1_power': [14.369810000000001]} - + golden_data = {'delay_hl': [1.718183], + 'delay_lh': [1.718183], + 'leakage_power': 0.1342958, + 'min_period': 3.75, + 'read0_power': [14.1499], + 'read1_power': [13.639719999999999], + 'slew_hl': [0.7794919], + 'slew_lh': [0.7794919], + 'write0_power': [15.978829999999999], + 'write1_power': [14.128079999999999]} else: self.assertTrue(False) # other techs fail diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 84d1f2db..77ddda76 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -345,11 +345,11 @@ spice["msflop_leakage"] = 1 # Leakage power of flop in nW spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transition_prob"] = .5 # Transition probability of inverter. -spice["inv_transition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. +spice["flop_transition_prob"] = 0.5 # Transition probability of inverter. +spice["inv_transition_prob"] = 0.5 # Transition probability of inverter. +spice["nand2_transition_prob"] = 0.1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = 0.1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = 0.1875 # Transition probability of 2-input nor. #Parameters related to sense amp enable timing and delay chain/RBL sizing parameter['le_tau'] = 2.25 #In pico-seconds. @@ -357,10 +357,10 @@ parameter['cap_relative_per_ff'] = 7.5 #Units of Relative Capacitance/ Femt parameter["dff_clk_cin"] = 30.6 #relative capacitance parameter["6tcell_wl_cin"] = 3 #relative capacitance parameter["min_inv_para_delay"] = 2.4 #Tau delay units -parameter["sa_en_pmos_size"] = .72 #micro-meters -parameter["sa_en_nmos_size"] = .27 #micro-meters -parameter["sa_inv_pmos_size"] = .54 #micro-meters -parameter["sa_inv_nmos_size"] = .27 #micro-meters +parameter["sa_en_pmos_size"] = 0.72 #micro-meters +parameter["sa_en_nmos_size"] = 0.27 #micro-meters +parameter["sa_inv_pmos_size"] = 0.54 #micro-meters +parameter["sa_inv_nmos_size"] = 0.27 #micro-meters parameter['bitcell_drain_cap'] = 0.1 #In Femto-Farad, approximation of drain capacitance ################################################### diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index fb7524c1..2d9abe16 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -284,26 +284,22 @@ spice["msflop_leakage"] = 1 # Leakage power of flop in nW spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transition_prob"] = .5 # Transition probability of inverter. -spice["inv_transition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. +spice["flop_transition_prob"] = 0.5 # Transition probability of inverter. +spice["inv_transition_prob"] = 0.5 # Transition probability of inverter. +spice["nand2_transition_prob"] = 0.1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = 0.1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = 0.1875 # Transition probability of 2-input nor. #Logical Effort relative values for the Handmade cells parameter['le_tau'] = 23 #In pico-seconds. -parameter["min_inv_para_delay"] = .73 #In relative delay units -parameter['cap_relative_per_ff'] = .91 #Units of Relative Capacitance/ Femto-Farad -parameter["static_delay_stages"] = 4 -parameter["static_fanout_per_stage"] = 3 -parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]] +parameter["min_inv_para_delay"] = 0.73 #In relative delay units +parameter['cap_relative_per_ff'] = 0.91 #Units of Relative Capacitance/ Femto-Farad parameter["dff_clk_cin"] = 27.5 #In relative capacitance units parameter["6tcell_wl_cin"] = 2 #In relative capacitance units parameter["sa_en_pmos_size"] = 24*_lambda_ parameter["sa_en_nmos_size"] = 9*_lambda_ parameter["sa_inv_pmos_size"] = 18*_lambda_ parameter["sa_inv_nmos_size"] = 9*_lambda_ -parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance ###################################################