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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
make contacts perpendicular to power rails to avoid drc violations
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@@ -368,7 +368,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'gnd' in top:
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inst = self.dummy_row_insts[1]
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if 'gnd' in inst.mod.pins:
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@@ -378,7 +379,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'vdd' in bottom:
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inst = self.dummy_row_insts[0]
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if 'vdd' in inst.mod.pins:
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@@ -388,7 +390,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'gnd' in bottom:
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inst = self.dummy_row_insts[0]
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if 'gnd' in inst.mod.pins:
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@@ -398,7 +401,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]))
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'vdd' in left:
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inst = self.dummy_col_insts[0]
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if 'vdd' in inst.mod.pins:
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@@ -408,7 +412,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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offset = vector(supply_pin.center()[0], array_pin.center()[1]),
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directions=("H", "H"))
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if 'gnd' in left:
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inst = self.dummy_col_insts[0]
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if 'gnd' in inst.mod.pins:
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@@ -418,7 +423,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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offset = vector(supply_pin.center()[0], array_pin.center()[1]),
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directions=("H", "H"))
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if 'vdd' in right:
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inst = self.dummy_col_insts[1]
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if 'vdd' in inst.mod.pins:
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@@ -428,7 +434,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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offset = vector(supply_pin.center()[0], array_pin.center()[1]),
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directions=("H", "H"))
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if 'gnd' in right:
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inst = self.dummy_col_insts[1]
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if 'gnd' in inst.mod.pins:
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@@ -438,7 +445,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(supply_pin.center()[0], array_pin.center()[1]))
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offset = vector(supply_pin.center()[0], array_pin.center()[1]),
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directions=("H", "H"))
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def route_unused_wordlines(self):
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"""
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