mirror of https://github.com/VLSIDA/OpenRAM.git
622 lines
29 KiB
Python
622 lines
29 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base import vector
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from openram.base import contact
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from openram.sram_factory import factory
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from openram.tech import drc, spice
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from openram.tech import cell_properties as props
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from openram.tech import connect_ring_bottom, connect_ring_left, connect_ring_right, connect_ring_top
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from openram.tech import power_ring_top, power_ring_bottom, power_ring_left, power_ring_right
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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class capped_replica_bitcell_array(bitcell_base_array):
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"""
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Creates a replica bitcell array then adds the row and column caps to all
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sides of a bitcell array.
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"""
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def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
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super().__init__(name, rows, cols, column_offset=0, row_offset=0)
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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cols,
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rbl,
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left_rbl,
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right_rbl))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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if rbl is not None:
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self.rbl = rbl
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else:
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self.rbl = [0] * len(self.all_ports)
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# This specifies which RBL to put on the left or right by port number
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# This could be an empty list
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if left_rbl is not None:
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self.left_rbl = left_rbl
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else:
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self.left_rbl = []
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# This could be an empty list
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if right_rbl is not None:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[]
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self.rbls = self.left_rbl + self.right_rbl
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = sum(self.rbl) + 2
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# If we aren't using row/col caps, then we need to use the bitcell
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#if not self.cell.end_caps:
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# self.extra_rows += 2
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def add_modules(self):
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""" Array and cap rows/columns """
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self.replica_bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.column_size,
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rows=self.row_size,
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rbl=self.rbl,
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column_offset=1,
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row_offset=1,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl)
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# Dummy Row or Col Cap, depending on bitcell array properties
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col_cap_module_type = ("col_cap_array" if self.cell.end_caps else "dummy_array")
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# TODO: remove redundancy from arguments in pairs below (top/bottom, left/right)
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# for example, cols takes the same value for top/bottom
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self.col_cap_top = factory.create(module_type=col_cap_module_type,
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cols=self.column_size + len(self.rbls),
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1,
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row_offset=self.row_size+ self.extra_rows + 1, #add 1 to account for bottom col_cap
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mirror=0,
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location="top",
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl)
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self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
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cols=self.column_size + len(self.rbls),
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1,
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row_offset=0,
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mirror=(1+self.row_size+self.extra_rows) % 2,
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location="bottom",
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl)
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# Dummy Col or Row Cap, depending on bitcell array properties
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row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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rows=self.row_size + self.extra_rows,
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column_offset=0,
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row_offset=0,
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location="left")
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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rows=self.row_size + self.extra_rows,
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column_offset=1 + len(self.left_rbl) + self.column_size + len(self.right_rbl),
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row_offset=0,
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location="right")
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def add_pins(self):
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# Arrays are always:
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# bitlines (column first then port order)
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# word lines (row first then port order)
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# dummy wordlines
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# replica wordlines
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# regular wordlines (bottom to top)
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# # dummy bitlines
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# replica bitlines (port order)
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# regular bitlines (left to right port order)
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#
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# vdd
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# gnd
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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# these four are only included for compatibility with other modules
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self.bitline_names = self.replica_bitcell_array.bitline_names
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self.all_bitline_names = self.replica_bitcell_array.all_bitline_names
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self.rbl_bitline_names = self.replica_bitcell_array.rbl_bitline_names
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self.all_rbl_bitline_names = self.replica_bitcell_array.all_rbl_bitline_names
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# this one is actually used (obviously)
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self.bitline_pin_list = self.replica_bitcell_array.bitline_pin_list
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self.add_pin_list(self.bitline_pin_list, "INOUT")
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def add_wordline_pins(self):
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# some of these are just included for compatibility with modules instantiating this module
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self.rbl_wordline_names = self.replica_bitcell_array.rbl_wordline_names
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self.all_rbl_wordline_names = self.replica_bitcell_array.all_rbl_wordline_names
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self.wordline_names = self.replica_bitcell_array.wordline_names
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self.all_wordline_names = self.replica_bitcell_array.all_wordline_names
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self.used_wordline_names = self.replica_bitcell_array.used_wordline_names
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self.unused_wordline_names = self.replica_bitcell_array.unused_wordline_names
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self.replica_array_wordline_names_with_grounded_wls = ["gnd" if x in self.unused_wordline_names else x for x in self.replica_bitcell_array.wordline_pin_list]
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# Left/right row caps cover the full array height. Pad with gnd so the
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# netlist list length matches the row cap (replica in the center); do
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# not use col cap wordline heuristics.
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n_rowcap_wl = len(self.row_cap_left.get_wordline_names())
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n_rba_wl = len(self.replica_array_wordline_names_with_grounded_wls)
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self.wordline_pin_list = []
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if self.rbls:
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self.wordline_pin_list.extend(["gnd"] * len(self.rbls))
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self.wordline_pin_list.extend(self.replica_array_wordline_names_with_grounded_wls)
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if self.rbls:
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self.wordline_pin_list.extend(["gnd"] * len(self.rbls))
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self.add_pin_list(self.used_wordline_names, "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.supplies = ["vdd", "gnd"]
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# Main array
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self.replica_bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
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mod=self.replica_bitcell_array)
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self.connect_inst(self.bitline_pin_list + self.replica_array_wordline_names_with_grounded_wls + self.supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap_bottom,))
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self.connect_inst(self.bitline_pin_list + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap_top))
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self.connect_inst(self.bitline_pin_list + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.wordline_pin_list + self.supplies)
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#print(self.dummy_col_insts[0].mod.pins)
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#print(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.wordline_pin_list + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.wordline_pin_list + self.supplies)
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# bitcell array needed for some offset calculations
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self.bitcell_array_inst = self.replica_bitcell_array.bitcell_array_inst
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def create_layout(self):
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# This creates space for the unused wordline connections as well as the
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# row-based or column based power and ground lines.
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self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
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self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
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# Everything is computed with the replica array
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self.replica_bitcell_array_inst.place(offset=0)
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self.add_end_caps()
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ll = vector(-1 * self.dummy_col_insts[0].width, -1 * self.dummy_row_insts[0].height)
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self.translate_all(ll)
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self.capped_rba_width = self.dummy_col_insts[0].width + self.dummy_row_insts[0].width + self.dummy_col_insts[1].width
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self.capped_rba_height = self.dummy_col_insts[0].height
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self.route_power_ring(self.supply_stack[2], self.supply_stack[0])
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self.route_supplies()
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self.route_unused_wordlines()
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self.reset_coordinates()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def route_power_ring(self, v_layer, h_layer):
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self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height))
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# add_power_ring uses one shared ring width/pitch for both horizontal and
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# vertical rails, so satisfy DRC requirements of both layers.
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v_layer_width = drc("minwidth_{}".format(v_layer))
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h_layer_width = drc("minwidth_{}".format(h_layer))
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self.supply_rail_width = max(v_layer_width, h_layer_width)
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v_layer_space = drc("{}_to_{}".format(v_layer, v_layer))
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h_layer_space = drc("{}_to_{}".format(h_layer, h_layer))
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# Pitch is centerline-to-centerline rail offset in add_power_ring.
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# Prefer technology routing pitch so ring placement aligns with the
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# routing/via grid, but never violate same-layer spacing.
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drc_pitch = self.supply_rail_width + max(v_layer_space, h_layer_space)
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tech_pitch = max(getattr(self, "{}_pitch".format(v_layer)),
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getattr(self, "{}_pitch".format(h_layer)))
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self.supply_rail_pitch = max(drc_pitch, tech_pitch)
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self.add_power_ring(v_layer=v_layer, h_layer=h_layer, top=power_ring_top, bottom=power_ring_bottom, left=power_ring_left, right=power_ring_right)
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def get_main_array_top(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_top()
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def get_main_array_bottom(self):
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return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_bottom()
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def get_main_array_left(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_left()
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def get_main_array_right(self):
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return self.replica_bitcell_array_inst.lx() + self.replica_bitcell_array.get_main_array_right()
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#FIXME: these names need to be changed to reflect what they're actually returning
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def get_replica_top(self):
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return self.dummy_row_insts[1].by()
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def get_replica_bottom(self):
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return self.dummy_row_insts[0].uy()
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def get_replica_left(self):
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return self.dummy_col_insts[0].lx()
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def get_replica_right(self):
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return self.dummy_col_insts[1].rx()
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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# must add the offset of the instance
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offsets = [self.replica_bitcell_array_inst.lx() + x for x in self.replica_bitcell_array.get_column_offsets()]
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return offsets
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def add_end_caps(self):
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""" Add dummy cells or end caps around the array """
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# Far top dummy row
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offset = self.replica_bitcell_array_inst.ul()
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self.dummy_row_insts[1].place(offset=offset)
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# Far bottom dummy row
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dummy_row_height = vector(0, self.dummy_row_insts[0].height)
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offset = self.replica_bitcell_array_inst.ll() - dummy_row_height
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self.dummy_row_insts[0].place(offset=offset)
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# Far left dummy col
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dummy_col_width = vector(self.dummy_col_insts[0].width, 0)
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offset = self.dummy_row_insts[0].ll() - dummy_col_width
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if self.dummy_col_insts[0].mod.cell.has_corners is False:
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offset += vector(0, dummy_row_height.y)
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self.dummy_col_insts[0].place(offset=offset)
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# Far right dummy col
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offset = self.dummy_row_insts[0].lr()
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if self.dummy_col_insts[0].mod.cell.has_corners is False:
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offset += vector(0, dummy_row_height.y)
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self.dummy_col_insts[1].place(offset=offset)
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def add_layout_pins(self):
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for pin_name in self.used_wordline_names + self.bitline_pin_list:
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pin = self.replica_bitcell_array_inst.get_pin(pin_name)
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if "wl" in pin_name:
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# wordlines
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pin_offset = pin.ll().scale(0, 1)
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pin_width = self.capped_rba_width
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pin_height = pin.height()
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else:
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# bitlines
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pin_offset = pin.ll().scale(1, 0)
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pin_width = pin.width()
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pin_height = self.capped_rba_height
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin_offset,
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width=pin_width,
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height=pin_height)
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def route_supplies(self):
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if OPTS.bitcell == "pbitcell":
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bitcell = factory.create(module_type="pbitcell")
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else:
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bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
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top = connect_ring_top
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bottom = connect_ring_bottom
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left = connect_ring_left
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right = connect_ring_right
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if 'vdd' in top:
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inst = self.dummy_row_insts[1]
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if 'vdd' in inst.mod.pins:
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array_pins = inst.get_pins('vdd')
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for array_pin in array_pins:
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supply_pin = self.top_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'gnd' in top:
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inst = self.dummy_row_insts[1]
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if 'gnd' in inst.mod.pins:
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array_pins = inst.get_pins('gnd')
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for array_pin in array_pins:
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supply_pin = self.top_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'vdd' in bottom:
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inst = self.dummy_row_insts[0]
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if 'vdd' in inst.mod.pins:
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array_pins = inst.get_pins('vdd')
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for array_pin in array_pins:
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supply_pin = self.bottom_vdd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'gnd' in bottom:
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inst = self.dummy_row_insts[0]
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if 'gnd' in inst.mod.pins:
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array_pins = inst.get_pins('gnd')
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for array_pin in array_pins:
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supply_pin = self.bottom_gnd_pin
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self.add_path(array_pin.layer, [array_pin.center(), vector(array_pin.center()[0], supply_pin.center()[1])])
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self.add_via_stack_center(from_layer = array_pin.layer,
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to_layer = supply_pin.layer,
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offset = vector(array_pin.center()[0], supply_pin.center()[1]),
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directions=("V", "V"))
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if 'vdd' in left:
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inst = self.dummy_col_insts[0]
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if 'vdd' in inst.mod.pins:
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array_pins = inst.get_pins('vdd')
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for array_pin in array_pins:
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supply_pin = self.left_vdd_pin
|
|
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
|
self.add_via_stack_center(from_layer = array_pin.layer,
|
|
to_layer = supply_pin.layer,
|
|
offset = vector(supply_pin.center()[0], array_pin.center()[1]),
|
|
directions=("H", "H"))
|
|
if 'gnd' in left:
|
|
inst = self.dummy_col_insts[0]
|
|
if 'gnd' in inst.mod.pins:
|
|
array_pins = inst.get_pins('gnd')
|
|
for array_pin in array_pins:
|
|
supply_pin = self.left_gnd_pin
|
|
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
|
self.add_via_stack_center(from_layer = array_pin.layer,
|
|
to_layer = supply_pin.layer,
|
|
offset = vector(supply_pin.center()[0], array_pin.center()[1]),
|
|
directions=("H", "H"))
|
|
if 'vdd' in right:
|
|
inst = self.dummy_col_insts[1]
|
|
if 'vdd' in inst.mod.pins:
|
|
array_pins = inst.get_pins('vdd')
|
|
for array_pin in array_pins:
|
|
supply_pin = self.right_vdd_pin
|
|
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
|
self.add_via_stack_center(from_layer = array_pin.layer,
|
|
to_layer = supply_pin.layer,
|
|
offset = vector(supply_pin.center()[0], array_pin.center()[1]),
|
|
directions=("H", "H"))
|
|
if 'gnd' in right:
|
|
inst = self.dummy_col_insts[1]
|
|
if 'gnd' in inst.mod.pins:
|
|
array_pins = inst.get_pins('gnd')
|
|
for array_pin in array_pins:
|
|
supply_pin = self.right_gnd_pin
|
|
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
|
|
self.add_via_stack_center(from_layer = array_pin.layer,
|
|
to_layer = supply_pin.layer,
|
|
offset = vector(supply_pin.center()[0], array_pin.center()[1]),
|
|
directions=("H", "H"))
|
|
|
|
def route_unused_wordlines(self):
|
|
"""
|
|
Connect the unused RBL and dummy wordlines to gnd
|
|
"""
|
|
# This grounds all the dummy row word lines
|
|
for inst in self.dummy_row_insts:
|
|
for wl_name in inst.mod.get_wordline_names():
|
|
pin = inst.get_pin(wl_name)
|
|
self.connect_side_pin(pin, "left", self.left_gnd_pin.cx())
|
|
self.connect_side_pin(pin, "right", self.right_gnd_pin.cx())
|
|
|
|
# Ground the unused replica wordlines
|
|
for wl_name in self.unused_wordline_names:
|
|
pin = self.replica_bitcell_array_inst.get_pin(wl_name)
|
|
self.connect_side_pin(pin, "left", self.left_gnd_pin.cx())
|
|
self.connect_side_pin(pin, "right", self.right_gnd_pin.cx())
|
|
|
|
def route_side_pin(self, name, side, offset_multiple=1):
|
|
"""
|
|
Routes a vertical or horizontal pin on the side of the bbox.
|
|
The multiple specifies how many track offsets to be away from the side assuming
|
|
(0,0) (self.width, self.height)
|
|
"""
|
|
if side in ["left", "right"]:
|
|
return self.route_vertical_side_pin(name, side, offset_multiple)
|
|
elif side in ["top", "bottom", "bot"]:
|
|
return self.route_horizontal_side_pin(name, side, offset_multiple)
|
|
else:
|
|
debug.error("Invalid side {}".format(side), -1)
|
|
|
|
def route_vertical_side_pin(self, name, side, offset_multiple=1):
|
|
"""
|
|
Routes a vertical pin on the side of the bbox.
|
|
"""
|
|
if side == "left":
|
|
bot_loc = vector(-offset_multiple * self.vertical_pitch, 0)
|
|
top_loc = vector(-offset_multiple * self.vertical_pitch, self.height)
|
|
elif side == "right":
|
|
bot_loc = vector(self.width + offset_multiple * self.vertical_pitch, 0)
|
|
top_loc = vector(self.width + offset_multiple * self.vertical_pitch, self.height)
|
|
|
|
layer = self.supply_stack[2]
|
|
top_via = contact(layer_stack=self.supply_stack,
|
|
directions=("H", "H"))
|
|
|
|
self.add_layout_pin_segment_center(text=name,
|
|
layer=layer,
|
|
start=bot_loc,
|
|
end=top_loc,
|
|
width=top_via.second_layer_width)
|
|
|
|
return (bot_loc, top_loc)
|
|
|
|
def route_horizontal_side_pin(self, name, side, offset_multiple=1):
|
|
"""
|
|
Routes a horizontal pin on the side of the bbox.
|
|
"""
|
|
if side in ["bottom", "bot"]:
|
|
left_loc = vector(0, -offset_multiple * self.horizontal_pitch)
|
|
right_loc = vector(self.width, -offset_multiple * self.horizontal_pitch)
|
|
elif side == "top":
|
|
left_loc = vector(0, self.height + offset_multiple * self.horizontal_pitch)
|
|
right_loc = vector(self.width, self.height + offset_multiple * self.horizontal_pitch)
|
|
|
|
layer = self.supply_stack[0]
|
|
side_via = contact(layer_stack=self.supply_stack,
|
|
directions=("V", "V"))
|
|
|
|
self.add_layout_pin_segment_center(text=name,
|
|
layer=layer,
|
|
start=left_loc,
|
|
end=right_loc,
|
|
width=side_via.first_layer_height)
|
|
|
|
return (left_loc, right_loc)
|
|
|
|
def connect_side_pin(self, pin, side, offset):
|
|
"""
|
|
Used to connect a pin to the a horizontal or vertical strap
|
|
offset gives the location of the strap
|
|
"""
|
|
if side in ["left", "right"]:
|
|
self.connect_vertical_side_pin(pin, offset)
|
|
elif side in ["top", "bottom", "bot"]:
|
|
self.connect_horizontal_side_pin(pin, offset)
|
|
else:
|
|
debug.error("Invalid side {}".format(side), -1)
|
|
|
|
def connect_horizontal_side_pin(self, pin, yoffset):
|
|
"""
|
|
Used to connect a pin to the top/bottom horizontal straps
|
|
"""
|
|
cell_loc = pin.center()
|
|
pin_loc = vector(cell_loc.x, yoffset)
|
|
|
|
# Place the pins a track outside of the array
|
|
self.add_via_stack_center(offset=pin_loc,
|
|
from_layer=pin.layer,
|
|
to_layer=self.supply_stack[0],
|
|
directions=("V", "V"))
|
|
|
|
# Add a path to connect to the array
|
|
self.add_path(pin.layer, [cell_loc, pin_loc])
|
|
|
|
def connect_vertical_side_pin(self, pin, xoffset):
|
|
"""
|
|
Used to connect a pin to the left/right vertical straps
|
|
"""
|
|
cell_loc = pin.center()
|
|
pin_loc = vector(xoffset, cell_loc.y)
|
|
|
|
# Place the pins a track outside of the array
|
|
self.add_via_stack_center(offset=pin_loc,
|
|
from_layer=pin.layer,
|
|
to_layer=self.supply_stack[2],
|
|
directions=("H", "H"))
|
|
|
|
# Add a path to connect to the array
|
|
self.add_path(pin.layer, [cell_loc, pin_loc])
|
|
|
|
def analytical_power(self, corner, load):
|
|
"""Power of Bitcell array and bitline in nW."""
|
|
# Dynamic Power from Bitline
|
|
bl_wire = self.gen_bl_wire()
|
|
cell_load = 2 * bl_wire.return_input_cap()
|
|
bl_swing = OPTS.rbl_delay_percentage
|
|
freq = spice["default_event_frequency"]
|
|
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
|
|
|
# Calculate the bitcell power which currently only includes leakage
|
|
cell_power = self.cell.analytical_power(corner, load)
|
|
|
|
# Leakage power grows with entire array and bitlines.
|
|
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
|
cell_power.leakage * self.column_size * self.row_size)
|
|
return total_power
|
|
|
|
|
|
def gen_bl_wire(self):
|
|
if OPTS.netlist_only:
|
|
height = 0
|
|
else:
|
|
height = self.height
|
|
bl_pos = 0
|
|
bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
|
|
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
|
return bl_wire
|
|
|
|
def graph_exclude_bits(self, targ_row=None, targ_col=None):
|
|
"""
|
|
Excludes bits in column from being added to graph except target
|
|
"""
|
|
self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
|
|
|
def graph_exclude_replica_col_bits(self):
|
|
"""
|
|
Exclude all replica/dummy cells in the replica columns except the replica bit.
|
|
"""
|
|
self.replica_bitcell_array.graph_exclude_replica_col_bits()
|
|
|
|
def get_cell_name(self, inst_name, row, col):
|
|
"""
|
|
Gets the spice name of the target bitcell.
|
|
"""
|
|
return self.replica_bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.replica_bitcell_array_inst.name, row, col)
|
|
|
|
def clear_exclude_bits(self):
|
|
"""
|
|
Clears the bit exclusions
|
|
"""
|
|
self.replica_bitcell_array.clear_exclude_bits()
|