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Create RBL wordline buffer with correct polarity.

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This commit is contained in:
mrg
2020-09-17 14:45:49 -07:00
parent 392afd4d4b
commit c7d32089f3
10 changed files with 156 additions and 56 deletions
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compiler/modules/global_bitcell_array.py
+5 -1
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@@ -54,6 +54,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
""" Add the modules used in this design """
self.local_mods = []
# Special case of a single local array
# so it should contain the left and possibly right RBL
if len(self.column_sizes) == 1:
la = factory.create(module_type="local_bitcell_array",
rows=self.row_size,
@@ -66,19 +68,21 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
return
for i, cols in enumerate(self.column_sizes):
# Always add the left RBLs to the first subarray and the right RBLs to the last subarray
# Always add the left RBLs to the first subarray
if i == 0:
la = factory.create(module_type="local_bitcell_array",
rows=self.row_size,
cols=cols,
rbl=self.rbl,
left_rbl=[0])
# Add the right RBL to the last subarray
elif i == len(self.column_sizes) - 1 and len(self.all_ports) > 1:
la = factory.create(module_type="local_bitcell_array",
rows=self.row_size,
cols=cols,
rbl=self.rbl,
right_rbl=[1])
# Middle subarrays do not have any RBLs
else:
la = factory.create(module_type="local_bitcell_array",
rows=self.row_size,