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https://github.com/VLSIDA/OpenRAM.git
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Use fake sram in memchar
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@@ -0,0 +1,5 @@
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BSIM3V3.1 Parameter Check
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Model = p
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W = 6e-07, L = 8e-07
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Warning: Pd = 0 is less than W.
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Warning: Ps = 0 is less than W.
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@@ -0,0 +1,59 @@
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ERROR: file testutils.py: line 266: Mismatching files:
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file1=/tmp/openram_bugra_979_temp//sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
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file2=/openram/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
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ERROR: file testutils.py: line 268: MISMATCH Line (74):
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type (wmask){
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!=
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cell (sram____scnm_subm){
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ERROR: file testutils.py: line 268: MISMATCH Line (75):
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base_type : array;
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!=
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memory(){
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ERROR: file testutils.py: line 268: MISMATCH Line (76):
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data_type : bit;
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!=
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type : ram;
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ERROR: file testutils.py: line 268: MISMATCH Line (77):
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bit_width : ;
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!=
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address_width : ;
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ERROR: file testutils.py: line 268: MISMATCH Line (78):
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bit_from : ;
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!=
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word_width : ;
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ERROR: file testutils.py: line 268: MISMATCH Line (79):
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bit_to : ;
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!=
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}
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ERROR: file testutils.py: line 268: MISMATCH Line (80):
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}
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!=
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interface_timing : true;
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ERROR: file testutils.py: line 268: MISMATCH Line (81):
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!=
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dont_use : true;
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ERROR: file testutils.py: line 268: MISMATCH Line (82):
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cell (sram____scnm_subm){
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!=
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map_only : true;
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ERROR: file testutils.py: line 268: MISMATCH Line (83):
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memory(){
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!=
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dont_touch : true;
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ERROR: file testutils.py: line 268: MISMATCH Line (84):
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type : ram;
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!=
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area : ;
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