From c7975e32747e3bb67d5bf272615aeb4e5d84dbf2 Mon Sep 17 00:00:00 2001
From: Bugra Onal <onalbugra@gmail.com>
Date: Wed, 10 Aug 2022 11:58:52 -0700
Subject: [PATCH] Use fake sram in memchar

---
 compiler/characterizer/fake_sram.py |  6 +--
 compiler/memchar.py                 |  4 +-
 compiler/tests/b3v3_1check.log      |  5 +++
 compiler/tests/sram.log             | 59 +++++++++++++++++++++++++++++
 4 files changed, 68 insertions(+), 6 deletions(-)
 create mode 100644 compiler/tests/b3v3_1check.log
 create mode 100644 compiler/tests/sram.log

diff --git a/compiler/characterizer/fake_sram.py b/compiler/characterizer/fake_sram.py
index c114d790..689be714 100644
--- a/compiler/characterizer/fake_sram.py
+++ b/compiler/characterizer/fake_sram.py
@@ -1,4 +1,6 @@
 import sram_config
+import OPTS
+
 
 class fake_sram(sram_config.sram_config):
     """ This is an SRAM that doesn't actually create itself, just computes
@@ -12,10 +14,6 @@ class fake_sram(sram_config.sram_config):
         # TODO: Get width and height from gds bbox
         self.width = 0
         self.height = 0
-        #c = reload(__import__(OPTS.bitcell))
-        #self.mod_bitcell = getattr(c, OPTS.bitcell)
-        #self.bitcell = self.mod_bitcell()
-        # to get the row, col, etc.
         self.compute_sizes()
         self.setup_multiport_constants()
 
diff --git a/compiler/memchar.py b/compiler/memchar.py
index b5eb4909..ba6b25cf 100755
--- a/compiler/memchar.py
+++ b/compiler/memchar.py
@@ -49,8 +49,8 @@ c = sram_config(word_size=OPTS.word_size,
 OPTS.netlist_only = True
 OPTS.check_lvsdrc = False
 
-# Initialize and create the sram object
-from sram import sram
+# Initialize and create a fake sram object
+import fake_sran as sram
 s = sram(name=OPTS.output_name, sram_config=c)
 
 # Characterize the design
diff --git a/compiler/tests/b3v3_1check.log b/compiler/tests/b3v3_1check.log
new file mode 100644
index 00000000..6903570b
--- /dev/null
+++ b/compiler/tests/b3v3_1check.log
@@ -0,0 +1,5 @@
+BSIM3V3.1 Parameter Check
+Model = p
+W = 6e-07, L = 8e-07
+Warning: Pd = 0 is less than W.
+Warning: Ps = 0 is less than W.
diff --git a/compiler/tests/sram.log b/compiler/tests/sram.log
new file mode 100644
index 00000000..a5b407c5
--- /dev/null
+++ b/compiler/tests/sram.log
@@ -0,0 +1,59 @@
+ERROR: file testutils.py: line 266: Mismatching files:
+file1=/tmp/openram_bugra_979_temp//sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
+file2=/openram/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
+
+ERROR: file testutils.py: line 268: MISMATCH Line (74):
+    type (wmask){
+!=
+cell (sram____scnm_subm){
+
+ERROR: file testutils.py: line 268: MISMATCH Line (75):
+    base_type : array;
+!=
+    memory(){ 
+
+ERROR: file testutils.py: line 268: MISMATCH Line (76):
+    data_type : bit;
+!=
+    type : ram;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (77):
+    bit_width : ;
+!=
+    address_width : ;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (78):
+    bit_from : ;
+!=
+    word_width : ;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (79):
+    bit_to : ;
+!=
+    }
+
+ERROR: file testutils.py: line 268: MISMATCH Line (80):
+    }
+!=
+    interface_timing : true;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (81):
+
+!=
+    dont_use  : true;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (82):
+cell (sram____scnm_subm){
+!=
+    map_only   : true;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (83):
+    memory(){ 
+!=
+    dont_touch : true;
+
+ERROR: file testutils.py: line 268: MISMATCH Line (84):
+    type : ram;
+!=
+    area : ;
+