mirror of https://github.com/VLSIDA/OpenRAM.git
Finalize uniquify option for SRAMs
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parent
8095c72fc8
commit
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@ -81,8 +81,9 @@ class VlsiLayout:
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coordinatesRotate.extend((newX,newY))
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coordinatesRotate.extend((newX,newY))
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return coordinatesRotate
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return coordinatesRotate
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def prefixAll(self, prefix):
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def uniquify(self):
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new_structures = {}
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new_structures = {}
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prefix = self.rootStructureName + "_"
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for name in self.structures:
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for name in self.structures:
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if name != self.rootStructureName:
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if name != self.rootStructureName:
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@ -166,6 +166,9 @@ class options(optparse.Values):
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keep_temp = False
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keep_temp = False
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# Add a prefix of the root cell before every structure in the GDS
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# after outputting the GDS2
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uniquify = False
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# These are the default modules that can be over-riden
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# These are the default modules that can be over-riden
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bank_select = "bank_select"
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bank_select = "bank_select"
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@ -4,8 +4,8 @@ import sys
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from gdsMill import gdsMill
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from gdsMill import gdsMill
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if len(sys.argv) < 4:
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if len(sys.argv) < 4:
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print("Script to prefix every instance and structure to create a unique namespace.")
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print("Script to prefix every instance and structure with the root cell name to provide unique namespace.")
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print("Usage: {0} prefix in.gds out.gds".format(sys.argv[0]))
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print("Usage: {0} in.gds out.gds".format(sys.argv[0]))
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sys.exit(1)
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sys.exit(1)
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prefix = sys.argv[1]
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prefix = sys.argv[1]
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@ -15,7 +15,7 @@ gds = gdsMill.VlsiLayout()
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reader = gdsMill.Gds2reader(gds)
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reader = gdsMill.Gds2reader(gds)
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reader.loadFromFile(gds_file)
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reader.loadFromFile(gds_file)
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gds.prefixAll(prefix)
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gds.uniquify()
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writer = gdsMill.Gds2writer(gds)
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writer = gdsMill.Gds2writer(gds)
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writer.writeToFile(sys.argv[3])
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writer.writeToFile(sys.argv[3])
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@ -11,6 +11,7 @@ import debug
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import verify
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import verify
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from characterizer import functional
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from characterizer import functional
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from globals import OPTS, print_time
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from globals import OPTS, print_time
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import shutil
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class sram():
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class sram():
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@ -60,6 +61,21 @@ class sram():
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def gds_write(self, name):
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def gds_write(self, name):
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self.s.gds_write(name)
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self.s.gds_write(name)
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# This addresses problems with flat GDS namespaces when we
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# want to merge this SRAM with other SRAMs.
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if OPTS.uniquify:
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import gdsMill
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gds = gdsMill.VlsiLayout()
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reader = gdsMill.Gds2reader(gds)
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reader.loadFromFile(name)
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gds.uniquify()
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writer = gdsMill.Gds2writer(gds)
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unique_name = name.replace(".gds", "_unique.gds")
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writer.writeToFile(unique_name)
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shutil.move(unique_name, name)
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def verilog_write(self, name):
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def verilog_write(self, name):
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self.s.verilog_write(name)
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self.s.verilog_write(name)
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@ -84,9 +100,9 @@ class sram():
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debug.print_raw("SP: Writing to {0}".format(spname))
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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self.sp_write(spname)
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functional(self.s,
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functional(self.s,
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os.path.basename(spname),
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os.path.basename(spname),
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cycles=200,
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cycles=200,
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output_path=OPTS.output_path)
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output_path=OPTS.output_path)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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if not OPTS.netlist_only:
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if not OPTS.netlist_only:
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