From c69eb47a7a49c726fdcc8011848ce2d43aec8ea4 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Tue, 22 Jun 2021 16:13:33 -0700
Subject: [PATCH] Finalize uniquify option for SRAMs

---
 compiler/gdsMill/gdsMill/vlsiLayout.py |  3 ++-
 compiler/options.py                    | 15 +++++++++------
 compiler/prefixGDS.py                  |  6 +++---
 compiler/sram/sram.py                  | 24 ++++++++++++++++++++----
 4 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py
index 8e53f74c..8448fe0f 100644
--- a/compiler/gdsMill/gdsMill/vlsiLayout.py
+++ b/compiler/gdsMill/gdsMill/vlsiLayout.py
@@ -81,8 +81,9 @@ class VlsiLayout:
             coordinatesRotate.extend((newX,newY))
         return coordinatesRotate
 
-    def prefixAll(self, prefix):
+    def uniquify(self):
         new_structures = {}
+        prefix = self.rootStructureName + "_"
 
         for name in self.structures:
             if name != self.rootStructureName:
diff --git a/compiler/options.py b/compiler/options.py
index 89b6c1ce..f3c19283 100644
--- a/compiler/options.py
+++ b/compiler/options.py
@@ -60,7 +60,7 @@ class options(optparse.Values):
     rbl_delay_percentage = 0.5
 
     # Allow manual adjustment of the delay chain over automatic
-    auto_delay_chain_sizing = False 
+    auto_delay_chain_sizing = False
     delay_chain_stages = 9
     delay_chain_fanout_per_stage = 4
 
@@ -72,12 +72,12 @@ class options(optparse.Values):
     # This is the temp directory where all intermediate results are stored.
     try:
         # If user defined the temporary location in their environment, use it
-        
+
         openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP"))
-        
+
     except:
         openram_temp = "/tmp"
-        
+
     # This is the verbosity level to control debug information. 0 is none, 1
     # is minimal, etc.
     verbose_level = 0
@@ -136,7 +136,7 @@ class options(optparse.Values):
     pex_exe = None
     # For sky130, we need magic for filtering.
     magic_exe = None
-    
+
     # Number of threads to use
     num_threads = 1
     # Number of threads to use in ngspice/hspice
@@ -144,7 +144,7 @@ class options(optparse.Values):
 
     # Some tools (e.g. Xyce) use other separators like ":"
     hier_seperator = "."
-    
+
     # Should we print out the banner at startup
     print_banner = True
 
@@ -166,6 +166,9 @@ class options(optparse.Values):
 
     keep_temp = False
 
+    # Add a prefix of the root cell before every structure in the GDS
+    # after outputting the GDS2
+    uniquify = False
 
     # These are the default modules that can be over-riden
     bank_select = "bank_select"
diff --git a/compiler/prefixGDS.py b/compiler/prefixGDS.py
index dac063c8..e6bfdb40 100755
--- a/compiler/prefixGDS.py
+++ b/compiler/prefixGDS.py
@@ -4,8 +4,8 @@ import sys
 from gdsMill import gdsMill
 
 if len(sys.argv) < 4:
-    print("Script to prefix every instance and structure to create a unique namespace.")
-    print("Usage: {0} prefix in.gds out.gds".format(sys.argv[0]))
+    print("Script to prefix every instance and structure with the root cell name to provide unique namespace.")
+    print("Usage: {0} in.gds out.gds".format(sys.argv[0]))
     sys.exit(1)
 
 prefix = sys.argv[1]
@@ -15,7 +15,7 @@ gds = gdsMill.VlsiLayout()
 reader = gdsMill.Gds2reader(gds)
 reader.loadFromFile(gds_file)
 
-gds.prefixAll(prefix)
+gds.uniquify()
 
 writer = gdsMill.Gds2writer(gds)
 writer.writeToFile(sys.argv[3])
diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py
index 17107860..a7d825a8 100644
--- a/compiler/sram/sram.py
+++ b/compiler/sram/sram.py
@@ -11,6 +11,7 @@ import debug
 import verify
 from characterizer import functional
 from globals import OPTS, print_time
+import shutil
 
 
 class sram():
@@ -23,7 +24,7 @@ class sram():
     def __init__(self, sram_config, name):
 
         sram_config.set_local_config(self)
-                
+
         # reset the static duplicate name checker for unit tests
         # in case we create more than one SRAM
         from design import design
@@ -60,6 +61,21 @@ class sram():
     def gds_write(self, name):
         self.s.gds_write(name)
 
+        # This addresses problems with flat GDS namespaces when we
+        # want to merge this SRAM with other SRAMs.
+        if OPTS.uniquify:
+            import gdsMill
+            gds = gdsMill.VlsiLayout()
+            reader = gdsMill.Gds2reader(gds)
+            reader.loadFromFile(name)
+
+            gds.uniquify()
+
+            writer = gdsMill.Gds2writer(gds)
+            unique_name = name.replace(".gds", "_unique.gds")
+            writer.writeToFile(unique_name)
+            shutil.move(unique_name, name)
+
     def verilog_write(self, name):
         self.s.verilog_write(name)
 
@@ -84,9 +100,9 @@ class sram():
         debug.print_raw("SP: Writing to {0}".format(spname))
         self.sp_write(spname)
         functional(self.s,
-                  os.path.basename(spname),
-                  cycles=200,
-                  output_path=OPTS.output_path)
+                   os.path.basename(spname),
+                   cycles=200,
+                   output_path=OPTS.output_path)
         print_time("Spice writing", datetime.datetime.now(), start_time)
 
         if not OPTS.netlist_only: