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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 05:53:21 +02:00
Finalize uniquify option for SRAMs
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+9
-6
@@ -60,7 +60,7 @@ class options(optparse.Values):
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rbl_delay_percentage = 0.5
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# Allow manual adjustment of the delay chain over automatic
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auto_delay_chain_sizing = False
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auto_delay_chain_sizing = False
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delay_chain_stages = 9
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delay_chain_fanout_per_stage = 4
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@@ -72,12 +72,12 @@ class options(optparse.Values):
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# This is the temp directory where all intermediate results are stored.
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try:
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# If user defined the temporary location in their environment, use it
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openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP"))
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except:
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openram_temp = "/tmp"
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# This is the verbosity level to control debug information. 0 is none, 1
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# is minimal, etc.
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verbose_level = 0
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@@ -136,7 +136,7 @@ class options(optparse.Values):
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pex_exe = None
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# For sky130, we need magic for filtering.
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magic_exe = None
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# Number of threads to use
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num_threads = 1
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# Number of threads to use in ngspice/hspice
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@@ -144,7 +144,7 @@ class options(optparse.Values):
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# Some tools (e.g. Xyce) use other separators like ":"
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hier_seperator = "."
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# Should we print out the banner at startup
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print_banner = True
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@@ -166,6 +166,9 @@ class options(optparse.Values):
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keep_temp = False
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# Add a prefix of the root cell before every structure in the GDS
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# after outputting the GDS2
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uniquify = False
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# These are the default modules that can be over-riden
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bank_select = "bank_select"
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