mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed issue with sen delay measure getting mixed with voltage checks
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@ -185,8 +185,7 @@ class delay(simulation):
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self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
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self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name+"{}", "FALL", "RISE", measure_scale=1e9)
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_add_delay = True
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self.sen_meas.meta_add_delay = True
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self.dout_volt_meas.append(self.sen_meas)
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return self.dout_volt_meas
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return self.dout_volt_meas
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def create_read_bit_measures(self):
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def create_read_bit_measures(self):
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