Modify unit tests to reset options during init_openram so

that they don't use old parameters after a failure.

compiler/base/hierarchy_design.py

@@ -61,7 +61,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
 
     def DRC_LVS(self, final_verification=False):
         """Checks both DRC and LVS for a module"""
-        if OPTS.check_lvsdrc:
+        # Unit tests will check themselves.
+        # Do not run if disabled in options.
+        if not OPTS.is_unit_test and OPTS.check_lvsdrc:
             tempspice = OPTS.openram_temp + "/temp.sp"
             tempgds = OPTS.openram_temp + "/temp.gds"
             self.sp_write(tempspice)
@@ -73,7 +75,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
 
     def DRC(self):
         """Checks DRC for a module"""
-        if OPTS.check_lvsdrc:
+        # Unit tests will check themselves.
+        # Do not run if disabled in options.
+        if not OPTS.is_unit_test and OPTS.check_lvsdrc:
             tempgds = OPTS.openram_temp + "/temp.gds"
             self.gds_write(tempgds)
             debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
@@ -81,7 +85,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
 
     def LVS(self, final_verification=False):
         """Checks LVS for a module"""
-        if OPTS.check_lvsdrc:
+        # Unit tests will check themselves.
+        # Do not run if disabled in options.
+        if not OPTS.is_unit_test and OPTS.check_lvsdrc:
             tempspice = OPTS.openram_temp + "/temp.sp"
             tempgds = OPTS.openram_temp + "/temp.gds"
             self.sp_write(tempspice)

compiler/globals.py

@@ -9,12 +9,14 @@ import optparse
 import options
 import sys
 import re
+import copy
 import importlib
 
 USAGE = "Usage: openram.py [options] <config file>\nUse -h for help.\n"
 
 # Anonymous object that will be the options
 OPTS = options.options()
+CHECKPOINT_OPTS=None
 
 def parse_args():
     """ Parse the optional arguments for OpenRAM """
@@ -102,6 +104,7 @@ def check_versions():
 
 def init_openram(config_file, is_unit_test=True):
     """Initialize the technology, paths, simulators, etc."""
+
     check_versions()
 
     debug.info(1,"Initializing OpenRAM...")
@@ -112,6 +115,10 @@ def init_openram(config_file, is_unit_test=True):
 
     import_tech()
 
+    # Reset the static duplicate name checker for unit tests.
+    import hierarchy_design
+    hierarchy_design.hierarchy_design.name_map=[]
+    
 
 
 def get_tool(tool_type, preferences):
@@ -132,15 +139,25 @@ def get_tool(tool_type, preferences):
         return(None,"")
 
     
-
 def read_config(config_file, is_unit_test=True):
     """ 
     Read the configuration file that defines a few parameters. The
     config file is just a Python file that defines some config
-    options. 
+    options. This will only actually get read the first time. Subsequent
+    reads will just restore the previous copy (ask mrg)
     """
     global OPTS
-    
+    global CHECKPOINT_OPTS
+
+    # This is a hack. If we are running a unit test and have checkpointed
+    # the options, load them rather than reading the config file.
+    # This way, the configuration is reloaded at the start of every unit test.
+    # If a unit test fails, we don't have to worry about restoring the old config values
+    # that may have been tested.
+    if is_unit_test and CHECKPOINT_OPTS:
+        OPTS = copy.deepcopy(CHECKPOINT_OPTS)
+        return
+        
     # Create a full path relative to current dir unless it is already an abs path
     if not os.path.isabs(config_file):
         config_file = os.getcwd() + "/" +  config_file
@@ -164,6 +181,7 @@ def read_config(config_file, is_unit_test=True):
         # The command line will over-ride the config file
         # except in the case of the tech name! This is because the tech name
         # is sometimes used to specify the config file itself (e.g. unit tests)
+        # Note that if we re-read a config file, nothing will get read again!
         if not k in OPTS.__dict__ or k=="tech_name":
             OPTS.__dict__[k]=v
     
@@ -192,7 +210,10 @@ def read_config(config_file, is_unit_test=True):
             os.chmod(OPTS.output_path, 0o750)
     except:
         debug.error("Unable to make output directory.",-1)
-    
+
+    # Make a checkpoint of the options so we can restore
+    # after each unit test
+    CHECKPOINT_OPTS = copy.deepcopy(OPTS)
         
         
 def end_openram():
@@ -275,9 +296,6 @@ def import_tech():
 
     debug.info(2,"Importing technology: " + OPTS.tech_name)
 
-    # Set the tech to the config file we read in instead of the command line value.
-    OPTS.tech_name = OPTS.tech_name
-        
     # environment variable should point to the technology dir
     try:
         OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH"))

compiler/tests/01_library_drc_test.py

@@ -15,7 +15,8 @@ class library_drc_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-
+        OPTS.check_lvsdrc=True
+        
         (gds_dir, gds_files) = setup_files()
         drc_errors = 0
         debug.info(1, "\nPerforming DRC on: " + ", ".join(gds_files))

compiler/tests/02_library_lvs_test.py

@@ -14,6 +14,7 @@ class library_lvs_test(openram_test):
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import verify
+        OPTS.check_lvsdrc=True
         (gds_dir, sp_dir, allnames) = setup_files()
         lvs_errors = 0
         debug.info(1, "Performing LVS on: " + ", ".join(allnames))
@@ -28,7 +29,7 @@ class library_lvs_test(openram_test):
                 lvs_errors += 1
                 debug.error("Missing SPICE file {}".format(gds_name))
             lvs_errors += verify.run_lvs(f, gds_name, sp_name)
-            self.assertEqual(lvs_errors, 0)
+
         # fail if the error count is not zero
         self.assertEqual(lvs_errors, 0)
         globals.end_openram()

compiler/tests/03_contact_test.py

@@ -15,7 +15,6 @@ class contact_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import contact
 
@@ -43,7 +42,6 @@ class contact_test(openram_test):
             c = contact.contact(layer_stack, (3, 3))
             self.local_drc_check(c)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/03_path_test.py

@@ -15,8 +15,7 @@ class path_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
+        
-
         import path
         import tech
         import design
@@ -84,8 +83,6 @@ class path_test(openram_test):
         path.path(w, layer_stack, position_list)
         self.local_drc_check(w)
 
-        # return it back to it's normal state
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/03_ptx_1finger_nmos_test.py

@@ -15,7 +15,6 @@ class ptx_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ptx
         import tech
@@ -26,7 +25,6 @@ class ptx_test(openram_test):
                       tx_type="nmos")
         self.local_drc_check(fet)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 

compiler/tests/03_ptx_1finger_pmos_test.py

@@ -15,7 +15,6 @@ class ptx_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ptx
         import tech
@@ -26,7 +25,6 @@ class ptx_test(openram_test):
                       tx_type="pmos")
         self.local_drc_check(fet)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 

compiler/tests/03_ptx_3finger_nmos_test.py

@@ -15,7 +15,6 @@ class ptx_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ptx
         import tech
@@ -28,7 +27,6 @@ class ptx_test(openram_test):
                       connect_poly=True)
         self.local_drc_check(fet)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 

compiler/tests/03_ptx_3finger_pmos_test.py

@@ -15,7 +15,6 @@ class ptx_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ptx
         import tech
@@ -28,7 +27,6 @@ class ptx_test(openram_test):
                       connect_poly=True)
         self.local_drc_check(fet)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/03_ptx_4finger_nmos_test.py

@@ -15,7 +15,6 @@ class ptx_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ptx
         import tech
@@ -28,7 +27,6 @@ class ptx_test(openram_test):
                       connect_poly=True)
         self.local_drc_check(fet)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 

compiler/tests/03_ptx_4finger_pmos_test.py

@@ -15,7 +15,6 @@ class ptx_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ptx
         import tech
@@ -28,7 +27,6 @@ class ptx_test(openram_test):
                       connect_poly=True)
         self.local_drc_check(fet)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/03_wire_test.py

@@ -15,7 +15,6 @@ class wire_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import wire
         import tech
@@ -122,8 +121,6 @@ class wire_test(openram_test):
         wire.wire(w, layer_stack, position_list)
         self.local_drc_check(w)
 
-        # return it back to it's normal state
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/04_pbitcell_test.py

@@ -22,7 +22,6 @@ class pbitcell_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pbitcell
         import tech
@@ -67,9 +66,8 @@ class pbitcell_test(openram_test):
         tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=0)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
-        OPTS.bitcell = "bitcell"
+
 
 
 # instantiate a copy of the class to actually run the test

compiler/tests/04_pinv_10x_test.py

@@ -17,7 +17,6 @@ class pinv_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pinv
         import tech
@@ -26,7 +25,6 @@ class pinv_test(openram_test):
         tx = pinv.pinv(size=8)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()        
 
 

compiler/tests/04_pinv_1x_beta_test.py

@@ -17,7 +17,6 @@ class pinv_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pinv
         import tech
@@ -26,7 +25,6 @@ class pinv_test(openram_test):
         tx = pinv.pinv(size=1, beta=3)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()        
 
 # instantiate a copy of the class to actually run the test

compiler/tests/04_pinv_1x_test.py

@@ -16,7 +16,6 @@ class pinv_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
         
 
         import pinv
@@ -26,7 +25,6 @@ class pinv_test(openram_test):
         tx = pinv.pinv(size=1)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()        
 
 # instantiate a copy of the class to actually run the test

compiler/tests/04_pinv_2x_test.py

@@ -17,7 +17,6 @@ class pinv_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pinv
         import tech
@@ -26,7 +25,6 @@ class pinv_test(openram_test):
         tx = pinv.pinv(size=2)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()        
 
 

compiler/tests/04_pinvbuf_test.py

@@ -17,7 +17,6 @@ class pinvbuf_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pinvbuf
 
@@ -25,7 +24,6 @@ class pinvbuf_test(openram_test):
         a = pinvbuf.pinvbuf(4,8)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/04_pnand2_test.py

@@ -19,7 +19,6 @@ class pnand2_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pnand2
         import tech
@@ -28,7 +27,6 @@ class pnand2_test(openram_test):
         tx = pnand2.pnand2(size=1)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/04_pnand3_test.py

@@ -19,7 +19,6 @@ class pnand3_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pnand3
         import tech
@@ -28,7 +27,6 @@ class pnand3_test(openram_test):
         tx = pnand3.pnand3(size=1)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/04_pnor2_test.py

@@ -19,7 +19,6 @@ class pnor2_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import pnor2
         import tech
@@ -28,7 +27,6 @@ class pnor2_test(openram_test):
         tx = pnor2.pnor2(size=1)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/04_precharge_test.py

@@ -17,7 +17,6 @@ class precharge_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import precharge
         import tech
@@ -26,7 +25,6 @@ class precharge_test(openram_test):
         tx = precharge.precharge(name="precharge_driver", size=1)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/04_single_level_column_mux_test.py

@@ -19,7 +19,6 @@ class single_level_column_mux_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import single_level_column_mux
         import tech
@@ -28,7 +27,6 @@ class single_level_column_mux_test(openram_test):
         tx = single_level_column_mux.single_level_column_mux(tx_size=8)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/05_bitcell_array_test.py

@@ -19,7 +19,6 @@ class array_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import bitcell_array
 
@@ -27,7 +26,6 @@ class array_test(openram_test):
         a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=4)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copy of the class to actually run the test

compiler/tests/05_pbitcell_array_test.py

@@ -11,38 +11,32 @@ import globals
 from globals import OPTS
 import debug
 
-#@unittest.skip("SKIPPING 05_array_multiport_test")
+#@unittest.skip("SKIPPING 05_pbitcell_array_test")
-
+class pbitcell_array_test(openram_test):
-class array_multiport_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import bitcell_array
 
+        debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"
         OPTS.rw_ports = 2
         OPTS.r_ports = 2
         OPTS.w_ports = 2
-        
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
         self.local_check(a)
-        
+            
+        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
+        OPTS.bitcell = "pbitcell"
         OPTS.rw_ports = 2
         OPTS.r_ports = 0
         OPTS.w_ports = 2
-        
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
         a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
         self.local_check(a)
-        
 
-        OPTS.bitcell = "bitcell"
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copy of the class to actually run the test

compiler/tests/06_hierarchical_decoder_test.py

@@ -17,7 +17,6 @@ class hierarchical_decoder_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import hierarchical_decoder
         import tech
@@ -48,7 +47,6 @@ class hierarchical_decoder_test(openram_test):
         a = hierarchical_decoder.hierarchical_decoder(rows=512)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -17,7 +17,6 @@ class hierarchical_predecode2x4_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import hierarchical_predecode2x4 as pre
         import tech
@@ -26,7 +25,6 @@ class hierarchical_predecode2x4_test(openram_test):
         a = pre.hierarchical_predecode2x4()
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -17,7 +17,6 @@ class hierarchical_predecode3x8_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import hierarchical_predecode3x8 as pre
         import tech
@@ -26,7 +25,6 @@ class hierarchical_predecode3x8_test(openram_test):
         a = pre.hierarchical_predecode3x8()
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/07_single_level_column_mux_array_test.py

@@ -16,7 +16,6 @@ class single_level_column_mux_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import single_level_column_mux_array
         
@@ -32,7 +31,6 @@ class single_level_column_mux_test(openram_test):
         a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True        
         globals.end_openram()
         
 

compiler/tests/08_precharge_array_test.py

@@ -17,7 +17,6 @@ class precharge_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import precharge_array
         import tech
@@ -26,7 +25,6 @@ class precharge_test(openram_test):
         pc = precharge_array.precharge_array(columns=3)
         self.local_check(pc)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 

compiler/tests/08_wordline_driver_test.py

@@ -19,7 +19,6 @@ class wordline_driver_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import wordline_driver
         import tech
@@ -28,7 +27,6 @@ class wordline_driver_test(openram_test):
         tx = wordline_driver.wordline_driver(rows=8)
         self.local_check(tx)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/09_sense_amp_array_test.py

@@ -17,7 +17,6 @@ class sense_amp_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import sense_amp_array
 
@@ -30,7 +29,6 @@ class sense_amp_test(openram_test):
         a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/10_write_driver_array_test.py

@@ -17,7 +17,6 @@ class write_driver_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import write_driver_array
 
@@ -29,7 +28,6 @@ class write_driver_test(openram_test):
         a = write_driver_array.write_driver_array(columns=16, word_size=8)
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copy of the class to actually run the test

compiler/tests/11_dff_array_test.py

@@ -17,7 +17,6 @@ class dff_array_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import dff_array
 
@@ -33,7 +32,6 @@ class dff_array_test(openram_test):
         a = dff_array.dff_array(rows=3, columns=1)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/11_dff_buf_array_test.py

@@ -17,7 +17,6 @@ class dff_buf_array_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import dff_buf_array
 
@@ -33,7 +32,6 @@ class dff_buf_array_test(openram_test):
         a = dff_buf_array.dff_buf_array(rows=3, columns=1)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/11_dff_buf_test.py

@@ -17,7 +17,6 @@ class dff_buf_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import dff_buf
 
@@ -25,7 +24,6 @@ class dff_buf_test(openram_test):
         a = dff_buf.dff_buf(4, 8)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/11_dff_inv_array_test.py

@@ -17,7 +17,6 @@ class dff_inv_array_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import dff_inv_array
 
@@ -33,7 +32,6 @@ class dff_inv_array_test(openram_test):
         a = dff_inv_array.dff_inv_array(rows=3, columns=1)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/11_dff_inv_test.py

@@ -17,7 +17,6 @@ class dff_inv_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import dff_inv
 
@@ -25,7 +24,6 @@ class dff_inv_test(openram_test):
         a = dff_inv.dff_inv(4)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/11_ms_flop_array_test.py

@@ -17,7 +17,6 @@ class dff_array_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import ms_flop_array
 
@@ -29,7 +28,6 @@ class dff_array_test(openram_test):
         a = ms_flop_array.ms_flop_array(columns=16, word_size=8)
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/12_tri_gate_array_test.py

@@ -17,7 +17,6 @@ class tri_gate_array_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import tri_gate_array
 
@@ -29,7 +28,6 @@ class tri_gate_array_test(openram_test):
         a = tri_gate_array.tri_gate_array(columns=16, word_size=8)
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/13_delay_chain_test.py

@@ -17,7 +17,6 @@ class delay_chain_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import delay_chain
 
@@ -25,7 +24,6 @@ class delay_chain_test(openram_test):
         a = delay_chain.delay_chain(fanout_list=[4, 4, 4, 4])
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/14_replica_bitline_test.py

@@ -17,7 +17,6 @@ class replica_bitline_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import replica_bitline
 
@@ -34,7 +33,6 @@ class replica_bitline_test(openram_test):
         a = replica_bitline.replica_bitline(stages,fanout,rows)
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/16_control_logic_test.py

@@ -17,7 +17,6 @@ class control_logic_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import control_logic
         import tech
@@ -26,7 +25,6 @@ class control_logic_test(openram_test):
         a = control_logic.control_logic(num_rows=128)
         self.local_check(a)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/19_bank_select_test.py

@@ -17,7 +17,6 @@ class bank_select_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import bank_select
 
@@ -25,7 +24,6 @@ class bank_select_test(openram_test):
         a = bank_select.bank_select()
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/19_multi_bank_test.py

@@ -17,7 +17,6 @@ class multi_bank_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import bank
 
@@ -37,7 +36,6 @@ class multi_bank_test(openram_test):
         a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="bank4_multi")
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/19_single_bank_test.py

@@ -17,7 +17,6 @@ class single_bank_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import bank
 
@@ -38,7 +37,6 @@ class single_bank_test(openram_test):
         a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="bank4_single")
         self.local_check(a)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/20_sram_1bank_test.py

@@ -17,7 +17,6 @@ class sram_1bank_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import sram
 
@@ -37,7 +36,6 @@ class sram_1bank_test(openram_test):
         # a = sram.sram(word_size=2, num_words=128, num_banks=1, name="sram4")
         # self.local_check(a, final_verification=True)
         
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/20_sram_2bank_test.py

@@ -18,7 +18,6 @@ class sram_2bank_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import sram
 
@@ -38,7 +37,6 @@ class sram_2bank_test(openram_test):
         # a = sram.sram(word_size=2, num_words=256 num_banks=2, name="sram4")
         # self.local_check(a, final_verification=True)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/20_sram_4bank_test.py

@@ -18,7 +18,6 @@ class sram_4bank_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         global verify
         import verify
-        OPTS.check_lvsdrc = False
 
         import sram
 
@@ -38,7 +37,6 @@ class sram_4bank_test(openram_test):
         # a = sram.sram(word_size=2, num_words=256, num_banks=4, name="sram4")
         # self.local_check(a, final_verification=True)
 
-        OPTS.check_lvsdrc = True
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/21_hspice_delay_test.py

@@ -15,7 +15,6 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         
@@ -35,7 +34,6 @@ class timing_sram_test(openram_test):
                       num_banks=OPTS.num_banks,
                       name="sram1")
 
-        OPTS.check_lvsdrc = True
 
         tempspice = OPTS.openram_temp + "temp.sp"
         s.sp_write(tempspice)
@@ -85,12 +83,7 @@ class timing_sram_test(openram_test):
             else:
                 self.isclose(data[k],golden_data[k],0.15)
 
-                
-        # reset these options
-        OPTS.check_lvsdrc = True
-        OPTS.analytical_delay = True
         reload(characterizer)
-
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/21_hspice_setuphold_test.py

@@ -15,7 +15,6 @@ class timing_setup_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
 
@@ -59,8 +58,6 @@ class timing_setup_test(openram_test):
             else:
                 self.isclose(data[k],golden_data[k],0.15)
 
-        OPTS.check_lvsdrc = True
-        OPTS.analytical_delay = True
         reload(characterizer)
         globals.end_openram()
         

compiler/tests/21_ngspice_delay_test.py

@@ -15,7 +15,6 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
 
@@ -84,12 +83,7 @@ class timing_sram_test(openram_test):
             else:
                 self.isclose(data[k],golden_data[k],0.15)
 
-        # reset these options
-        OPTS.check_lvsdrc = True
-        OPTS.spice_name="hspice"
-        OPTS.analytical_delay = True
         reload(characterizer)
-
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/21_ngspice_setuphold_test.py

@@ -15,7 +15,6 @@ class timing_setup_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
 
@@ -58,12 +57,7 @@ class timing_setup_test(openram_test):
             else:
                 self.isclose(data[k],golden_data[k],0.15)
 
-        # reset these options
-        OPTS.check_lvsdrc = True
-        OPTS.spice_name="hspice"
-        OPTS.analytical_delay = True
         reload(characterizer)
-
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/22_pex_test.py

@@ -31,14 +31,12 @@ class sram_func_test(openram_test):
         import tech
 
         debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
-        OPTS.check_lvsdrc = False
+        global OPTS
         OPTS.use_pex = True
         s = sram.sram(word_size=OPTS.word_size,
                       num_words=OPTS.num_words,
                       num_banks=OPTS.num_banks,
                       name="test_sram1")
-        OPTS.check_lvsdrc = True
-        OPTS.use_pex = False
 
         tempspice = OPTS.openram_temp + "temp.sp"
         tempgds = OPTS.openram_temp + "temp.gds"
@@ -90,7 +88,7 @@ class sram_func_test(openram_test):
         self.assertTrue(round(value1) > 0.5 * tech.spice["supply_voltage"])
         self.assertTrue(round(value2) < 0.5 * tech.spice["supply_voltage"])
 
-        OPTS.check_lvsdrc = True
+
 
     def convert_voltage_unit(self, string):
         newstring = ""

compiler/tests/22_sram_func_test.py

@@ -16,8 +16,6 @@ class sram_func_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
-        OPTS.spice_name="" # Unset to use any simulator
         OPTS.analytical_delay = False
 
         # This is a hack to reload the characterizer __init__ with the spice version
@@ -36,8 +34,6 @@ class sram_func_test(openram_test):
                       num_banks=1,
                       name="sram_func_test")
 
-        OPTS.check_lvsdrc = True
-
         tempspice = OPTS.openram_temp + "temp.sp"
         s.sp_write(tempspice)
 
@@ -56,7 +52,7 @@ class sram_func_test(openram_test):
         feasible_period = d.find_feasible_period()
 
         os.remove(tempspice)
-        OPTS.analytical_delay = True
+
         reload(characterizer)
         globals.end_openram()
         

compiler/tests/23_lib_sram_model_test.py

@@ -15,7 +15,6 @@ class lib_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
 
         import sram
         from characterizer import lib
@@ -25,8 +24,7 @@ class lib_test(openram_test):
                       num_words=16,
                       num_banks=1,
                       name="sram_2_16_1_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = True
+        
-
         tempspice = OPTS.openram_temp + "temp.sp"
         s.sp_write(tempspice)
 

compiler/tests/23_lib_sram_prune_test.py

@@ -15,8 +15,6 @@ class lib_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
-        OPTS.spice_name="" # Unset to use any simulator
         OPTS.analytical_delay = False
         OPTS.trim_netlist = True
 
@@ -35,7 +33,6 @@ class lib_test(openram_test):
                       num_words=16,
                       num_banks=1,
                       name="sram_2_16_1_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = True
 
         tempspice = OPTS.openram_temp + "temp.sp"
         s.sp_write(tempspice)
@@ -54,7 +51,6 @@ class lib_test(openram_test):
             golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
             self.isapproxdiff(libname,golden,0.40)
 
-        OPTS.analytical_delay = True
         reload(characterizer)
         globals.end_openram()
         

compiler/tests/23_lib_sram_test.py

@@ -15,8 +15,6 @@ class lib_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = False
-        OPTS.spice_name="" # Unset to use any simulator
         OPTS.analytical_delay = False
         OPTS.trim_netlist = False
 
@@ -35,7 +33,6 @@ class lib_test(openram_test):
                       num_words=16,
                       num_banks=1,
                       name="sram_2_16_1_{0}".format(OPTS.tech_name))
-        OPTS.check_lvsdrc = True
 
         tempspice = OPTS.openram_temp + "temp.sp"
         s.sp_write(tempspice)
@@ -53,8 +50,6 @@ class lib_test(openram_test):
             golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
             self.isapproxdiff(libname,golden,0.40)
 
-        OPTS.analytical_delay = True
-        OPTS.trim_netlist = True
         reload(characterizer)
         globals.end_openram()
         

compiler/tests/24_lef_sram_test.py

@@ -15,8 +15,6 @@ class lef_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        # we will manually run lvs/drc
-        OPTS.check_lvsdrc = False
 
         import sram
 
@@ -26,8 +24,6 @@ class lef_test(openram_test):
                       num_banks=OPTS.num_banks,
                       name="sram_2_16_1_{0}".format(OPTS.tech_name))
 
-        OPTS.check_lvsdrc = True
-
         gdsfile = s.name + ".gds"
         leffile = s.name + ".lef"
         gdsname = OPTS.openram_temp + gdsfile

compiler/tests/25_verilog_sram_test.py

@@ -15,8 +15,6 @@ class verilog_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        # we will manually run lvs/drc
-        OPTS.check_lvsdrc = False
 
         import sram
 
@@ -26,8 +24,6 @@ class verilog_test(openram_test):
                       num_banks=OPTS.num_banks,
                       name="sram_2_16_1_{0}".format(OPTS.tech_name))
 
-        OPTS.check_lvsdrc = True
-
         vfile = s.name + ".v"
         vname = OPTS.openram_temp + vfile
         s.verilog_write(vname)

compiler/tests/regress.py

@@ -27,5 +27,6 @@ modules = map(__import__, moduleNames)
 suite = unittest.TestSuite()
 load = unittest.defaultTestLoader.loadTestsFromModule
 suite.addTests(map(load, modules))
+
 ret = not unittest.TextTestRunner(verbosity=2).run(suite).wasSuccessful()
 sys.exit(ret)

compiler/tests/testutils.py

@@ -1,5 +1,5 @@
 import unittest,warnings
-import sys,os,glob
+import sys,os,glob,copy
 sys.path.append(os.path.join(sys.path[0],".."))
 from globals import OPTS
 import debug
@@ -8,17 +8,23 @@ class openram_test(unittest.TestCase):
     """ Base unit test that we have some shared classes in. """
     
     def local_drc_check(self, w):
+
+        self.reset()
+
         tempgds = OPTS.openram_temp + "temp.gds"
         w.gds_write(tempgds)
         import verify
-        self.assertFalse(verify.run_drc(w.name, tempgds))
 
-        files = glob.glob(OPTS.openram_temp + '*')
+        result=verify.run_drc(w.name, tempgds)
-        for f in files:
+        if result != 0:
-            os.remove(f)        
+            self.fail("DRC failed: {}".format(a.name))
+
+        self.cleanup()
     
     def local_check(self, a, final_verification=False):
 
+        self.reset()
+        
         tempspice = OPTS.openram_temp + "temp.sp"
         tempgds = OPTS.openram_temp + "temp.gds"
 
@@ -27,13 +33,11 @@ class openram_test(unittest.TestCase):
 
         import verify
         result=verify.run_drc(a.name, tempgds)
-        self.reset()
         if result != 0:
             self.fail("DRC failed: {}".format(a.name))
 
             
         result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
-        self.reset()
         if result != 0:
             self.fail("LVS mismatch: {}".format(a.name))
 
@@ -49,9 +53,14 @@ class openram_test(unittest.TestCase):
                 os.remove(f)        
 
     def reset(self):
-        """ Reset the static duplicate name checker for unit tests """
+        """ 
+        Reset everything after each test.
+        """
+        # Reset the static duplicate name checker for unit tests.
         import hierarchy_design
         hierarchy_design.hierarchy_design.name_map=[]
+        
+
 
     def isclose(self, value1,value2,error_tolerance=1e-2):
         """ This is used to compare relative values. """