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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
restore netlist on memchar
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@@ -1130,15 +1130,17 @@ class delay(simulation):
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Netlist reduced for simulation.
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"""
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super().set_probe(probe_address, probe_data)
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self.prepare_netlist()
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def prepare_netlist(self):
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""" Prepare a trimmed netlist and regular netlist. """
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# Set up to trim the netlist here if that is enabled
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# TODO: Copy old netlist if memchar
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if OPTS.trim_netlist:
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self.trim_sp_file = "{0}trimmed.sp".format(self.output_path)
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self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True)
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# Only genrate spice when running openram process
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if OPTS.top_process == "openram":
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self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True)
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else:
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# The non-reduced netlist file when it is disabled
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self.trim_sp_file = "{0}sram.sp".format(self.output_path)
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@@ -1153,6 +1155,7 @@ class delay(simulation):
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"""Sets values which are dependent on the data address/bit being tested."""
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self.set_probe(probe_address, probe_data)
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self.prepare_netlist()
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self.create_graph()
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self.set_internal_spice_names()
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self.create_measurement_names()
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