From c4cf8134fe2e2cae14cc3db0111e2c959a07b2de Mon Sep 17 00:00:00 2001 From: Matthew Guthaus Date: Fri, 15 Nov 2019 18:47:59 +0000 Subject: [PATCH] Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. --- compiler/base/geometry.py | 6 +-- compiler/base/hierarchy_layout.py | 50 ++++++++++++++----- compiler/globals.py | 18 +++---- compiler/tests/01_library_drc_test.py | 3 +- compiler/tests/02_library_lvs_test.py | 3 +- compiler/tests/03_contact_test.py | 3 +- compiler/tests/03_path_test.py | 3 +- compiler/tests/03_ptx_1finger_nmos_test.py | 3 +- compiler/tests/03_ptx_1finger_pmos_test.py | 3 +- compiler/tests/03_ptx_3finger_nmos_test.py | 3 +- compiler/tests/03_ptx_3finger_pmos_test.py | 3 +- compiler/tests/03_ptx_4finger_nmos_test.py | 3 +- compiler/tests/03_ptx_4finger_pmos_test.py | 3 +- compiler/tests/03_wire_test.py | 3 +- compiler/tests/04_dummy_pbitcell_test.py | 3 +- compiler/tests/04_pand2_test.py | 3 +- compiler/tests/04_pand3_test.py | 3 +- compiler/tests/04_pbitcell_test.py | 3 +- compiler/tests/04_pbuf_test.py | 3 +- compiler/tests/04_pdriver_test.py | 3 +- compiler/tests/04_pinv_10x_test.py | 3 +- compiler/tests/04_pinv_1x_beta_test.py | 3 +- compiler/tests/04_pinv_1x_test.py | 3 +- compiler/tests/04_pinv_2x_test.py | 3 +- compiler/tests/04_pinvbuf_test.py | 3 +- compiler/tests/04_pnand2_test.py | 3 +- compiler/tests/04_pnand3_test.py | 3 +- compiler/tests/04_pnor2_test.py | 3 +- compiler/tests/04_precharge_test.py | 3 +- compiler/tests/04_replica_pbitcell_test.py | 3 +- .../tests/04_single_level_column_mux_test.py | 3 +- .../tests/05_bitcell_1rw_1r_array_test.py | 4 +- compiler/tests/05_bitcell_array_test.py | 3 +- compiler/tests/05_dummy_array_test.py | 3 +- compiler/tests/05_pbitcell_array_test.py | 3 +- .../tests/05_replica_pbitcell_array_test.py | 3 +- .../tests/06_hierarchical_decoder_test.py | 3 +- .../06_hierarchical_predecode2x4_test.py | 3 +- .../06_hierarchical_predecode3x8_test.py | 3 +- .../07_single_level_column_mux_array_test.py | 3 +- compiler/tests/08_precharge_array_test.py | 3 +- compiler/tests/08_wordline_driver_test.py | 3 +- compiler/tests/09_sense_amp_array_test.py | 3 +- compiler/tests/10_write_driver_array_test.py | 3 +- .../tests/10_write_driver_array_wmask_test.py | 5 +- .../tests/10_write_mask_and_array_test.py | 3 +- compiler/tests/11_dff_array_test.py | 3 +- compiler/tests/11_dff_buf_array_test.py | 3 +- compiler/tests/11_dff_buf_test.py | 3 +- compiler/tests/12_tri_gate_array_test.py | 3 +- compiler/tests/13_delay_chain_test.py | 3 +- .../14_replica_bitcell_1rw_1r_array_test.py | 3 +- .../tests/14_replica_bitcell_array_test.py | 3 +- compiler/tests/14_replica_column_test.py | 3 +- .../tests/16_control_logic_multiport_test.py | 3 +- compiler/tests/16_control_logic_test.py | 3 +- compiler/tests/18_port_address_test.py | 3 +- compiler/tests/18_port_data_test.py | 3 +- compiler/tests/18_port_data_wmask_test.py | 3 +- compiler/tests/19_bank_select_test.py | 3 +- compiler/tests/19_multi_bank_test.py | 3 +- compiler/tests/19_pmulti_bank_test.py | 3 +- compiler/tests/19_psingle_bank_test.py | 3 +- compiler/tests/19_single_bank_1rw_1r_test.py | 3 +- compiler/tests/19_single_bank_1w_1r_test.py | 3 +- compiler/tests/19_single_bank_test.py | 3 +- compiler/tests/19_single_bank_wmask_test.py | 3 +- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 5 +- .../20_psram_1bank_2mux_1rw_1w_wmask_test.py | 5 +- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 5 +- compiler/tests/20_psram_1bank_2mux_test.py | 5 +- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 5 +- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 3 +- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 5 +- compiler/tests/20_sram_1bank_2mux_test.py | 3 +- .../tests/20_sram_1bank_2mux_wmask_test.py | 5 +- .../20_sram_1bank_32b_1024_wmask_test.py | 5 +- compiler/tests/20_sram_1bank_4mux_test.py | 3 +- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 3 +- compiler/tests/20_sram_1bank_8mux_test.py | 3 +- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 3 +- compiler/tests/20_sram_1bank_nomux_test.py | 3 +- .../tests/20_sram_1bank_nomux_wmask_test.py | 5 +- compiler/tests/20_sram_2bank_test.py | 3 +- compiler/tests/21_hspice_delay_test.py | 3 +- compiler/tests/21_hspice_setuphold_test.py | 3 +- compiler/tests/21_model_delay_test.py | 3 +- compiler/tests/21_ngspice_delay_test.py | 3 +- compiler/tests/21_ngspice_setuphold_test.py | 3 +- .../tests/22_psram_1bank_2mux_func_test.py | 3 +- .../tests/22_psram_1bank_4mux_func_test.py | 3 +- .../tests/22_psram_1bank_8mux_func_test.py | 3 +- .../tests/22_psram_1bank_nomux_func_test.py | 3 +- .../tests/22_sram_1bank_2mux_func_test.py | 3 +- .../tests/22_sram_1bank_4mux_func_test.py | 3 +- .../tests/22_sram_1bank_8mux_func_test.py | 3 +- .../tests/22_sram_1bank_nomux_func_test.py | 3 +- .../22_sram_1rw_1r_1bank_nomux_func_test.py | 3 +- .../tests/22_sram_wmask_1w_1r_func_test.py | 3 +- compiler/tests/22_sram_wmask_func_test.py | 3 +- .../tests/23_lib_sram_model_corners_test.py | 3 +- compiler/tests/23_lib_sram_model_test.py | 3 +- compiler/tests/23_lib_sram_prune_test.py | 3 +- compiler/tests/23_lib_sram_test.py | 3 +- compiler/tests/24_lef_sram_test.py | 3 +- compiler/tests/25_verilog_sram_test.py | 3 +- compiler/tests/26_hspice_pex_pinv_test.py | 3 +- compiler/tests/26_ngspice_pex_pinv_test.py | 3 +- compiler/tests/26_pex_test.py | 3 +- compiler/tests/30_openram_back_end_test.py | 3 +- compiler/tests/30_openram_front_end_test.py | 3 +- 111 files changed, 272 insertions(+), 147 deletions(-) diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index f8eb03ab..cbc1d268 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -167,7 +167,7 @@ class instance(geometry): debug.info(4, "creating instance: " + self.name) - def get_blockages(self, layer, top=False): + def get_blockages(self, lpp, top=False): """ Retrieve blockages of all modules in this instance. Apply the transform of the instance placement to give absolute blockages.""" angle = math.radians(float(self.rotate)) @@ -191,11 +191,11 @@ class instance(geometry): if self.mod.is_library_cell: # Writes library cell blockages as shapes instead of a large metal blockage blockages = [] - blockages = self.mod.gds.getBlockages(layer) + blockages = self.mod.gds.getBlockages(lpp) for b in blockages: new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) else: - blockages = self.mod.get_blockages(layer) + blockages = self.mod.get_blockages(lpp) for b in blockages: new_blockages.append(self.transform_coords(b,self.offset, mirr, angle)) return new_blockages diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 503bd1d5..000e16ee 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -539,21 +539,21 @@ class layout(): Do not write the pins since they aren't obstructions. """ if type(layer)==str: - layer_num = techlayer[layer][0] + lpp = techlayer[layer] else: - layer_num = layer + lpp = layer blockages = [] for i in self.objs: - blockages += i.get_blockages(layer_num) + blockages += i.get_blockages(lpp) for i in self.insts: - blockages += i.get_blockages(layer_num) + blockages += i.get_blockages(lpp) # Must add pin blockages to non-top cells if not top_level: - blockages += self.get_pin_blockages(layer_num) + blockages += self.get_pin_blockages(lpp) return blockages - def get_pin_blockages(self, layer_num): + def get_pin_blockages(self, lpp): """ Return the pin shapes as blockages for non-top-level blocks. """ # FIXME: We don't have a body contact in ptx, so just ignore it for now import copy @@ -565,33 +565,57 @@ class layout(): for pin_name in pin_names: pin_list = self.get_pins(pin_name) for pin in pin_list: - if pin.layer_num==layer_num: + if pin.same_lpp(pin.lpp, lpp): blockages += [pin.rect] return blockages def create_horizontal_pin_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus of pins. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=True) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=False, + make_pins=True) def create_vertical_pin_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus of pins. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=True) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=True, + make_pins=True) def create_vertical_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=False) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=True, + make_pins=False) def create_horizontal_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus. """ - return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=False) + return self.create_bus(layer, + pitch, + offset, + names, + length, + vertical=False, + make_pins=False) def create_bus(self, layer, pitch, offset, names, length, vertical, make_pins): - """ + """ Create a horizontal or vertical bus. It can be either just rectangles, or actual layout pins. It returns an map of line center line positions indexed by name. - The other coordinate is a 0 since the bus provides a range. + The other coordinate is a 0 since the bus provides a range. TODO: combine with channel router. """ diff --git a/compiler/globals.py b/compiler/globals.py index eae61ba7..08ae4d96 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -282,13 +282,9 @@ def read_config(config_file, is_unit_test=True): # it is already not an abs path, make it one if not os.path.isabs(config_file): - try: - OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - except: - debug.error("$OPENRAM_HOME is not properly defined.", 1) - config_file = OPENRAM_HOME + "/tests/" + config_file + ".py" - debug.check(os.path.isfile(config_file), - "{} is not a valid config file".format(config_file)) + config_file = os.getcwd() + "/" + config_file + # Make it a python file if the base name was only given + config_file = re.sub(r'\.py$', "", config_file) # Expand the user if it is used @@ -297,16 +293,14 @@ def read_config(config_file, is_unit_test=True): # Add the path to the system path # so we can import things in the other directory dir_name = os.path.dirname(config_file) - file_name = os.path.basename(config_file) - # Remove the py from the module name - file_name = re.sub(r'\.py$', "", file_name) + module_name = os.path.basename(config_file) # Prepend the path to avoid if we are using the example config sys.path.insert(0, dir_name) # Import the configuration file of which modules to use debug.info(1, "Configuration file is " + config_file + ".py") try: - config = importlib.import_module(file_name) + config = importlib.import_module(module_name) except: debug.error("Unable to read configuration file: {0}".format(config_file),2) @@ -315,7 +309,7 @@ def read_config(config_file, is_unit_test=True): # except in the case of the tech name! This is because the tech name # is sometimes used to specify the config file itself (e.g. unit tests) # Note that if we re-read a config file, nothing will get read again! - if not k in OPTS.__dict__ or k == "tech_name": + if k not in OPTS.__dict__ or k == "tech_name": OPTS.__dict__[k] = v # Massage the output path to be an absolute one diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index b5578d1b..94e7b396 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -17,7 +17,8 @@ import debug class library_drc_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import verify (gds_dir, gds_files) = setup_files() diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 2bb4aa32..2916a3da 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -17,7 +17,8 @@ import debug class library_lvs_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import verify (gds_dir, sp_dir, allnames) = setup_files() diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 84e18d80..e43eeee3 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -18,7 +18,8 @@ import debug class contact_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]: stack_name = ":".join(map(str, layer_stack)) diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index a753e609..4cc1f942 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -17,7 +17,8 @@ import debug class path_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import wire_path import tech import design diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index a174ff54..81977458 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking min size NMOS with 1 finger") diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 50725055..bb995099 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking min size PMOS with 1 finger") diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 0f55bd23..bbfea153 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 484ae403..88b80321 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index d4b122c6..52d8f2f2 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index f4c5bfe1..3cdcc492 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -18,7 +18,8 @@ import debug class ptx_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 9c7f6c3d..0cd977f6 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -17,7 +17,8 @@ import debug class wire_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import wire import tech import design diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py index 64964067..a19145f5 100755 --- a/compiler/tests/04_dummy_pbitcell_test.py +++ b/compiler/tests/04_dummy_pbitcell_test.py @@ -18,7 +18,8 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import dummy_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index b2ee471e..7cb21615 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -18,7 +18,8 @@ import debug class pand2_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) global verify import verify diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py index 4a778b20..2efbdacf 100755 --- a/compiler/tests/04_pand3_test.py +++ b/compiler/tests/04_pand3_test.py @@ -18,7 +18,8 @@ import debug class pand3_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 16497ca9..e6b093b9 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -19,7 +19,8 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index e2990beb..847a2139 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -18,7 +18,8 @@ import debug class pbuf_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pbuf", size=8) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index bbb790ea..95865f84 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -18,7 +18,8 @@ import debug class pdriver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index e3c3b6a7..22da05db 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 124c31dd..fe91d339 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index cc240f22..d25192f5 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 430af7f7..b4419bc5 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -18,7 +18,8 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index fefb157f..0a32c7c4 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -18,7 +18,8 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 1873a38e..0f0f2a5d 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -18,7 +18,8 @@ import debug class pnand2_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index c8ea4174..be1ac294 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -18,7 +18,8 @@ import debug class pnand3_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index db93c64f..046fc6ab 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -18,7 +18,8 @@ import debug class pnor2_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index a9027ee7..3b0d2e0c 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -18,7 +18,8 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 1308ac56..1e075629 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -18,7 +18,8 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import replica_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 77c8a01c..07dada90 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -20,7 +20,8 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check single level column mux in single port debug.info(2, "Checking column mux") diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 1f96c469..6e757067 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -20,8 +20,8 @@ import debug class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 2c23d40f..f9bebaef 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -20,7 +20,8 @@ import debug class array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index 40b0436c..a10ee83d 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -16,7 +16,8 @@ import debug class dummy_row_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dummy row for 6t_cell") a = factory.create(module_type="dummy_array", rows=1, cols=4) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index cc9ee573..0e58da3a 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -19,7 +19,8 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/05_replica_pbitcell_array_test.py b/compiler/tests/05_replica_pbitcell_array_test.py index 1f66fe11..13204f0a 100755 --- a/compiler/tests/05_replica_pbitcell_array_test.py +++ b/compiler/tests/05_replica_pbitcell_array_test.py @@ -16,7 +16,8 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 3a407dc1..d4d68017 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -18,7 +18,8 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index cd730563..ddc9cec2 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -18,7 +18,8 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index b595cec8..4e4c5b9a 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -18,7 +18,8 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index cdf2aa47..09eeb98c 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -17,7 +17,8 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import single_level_column_mux_array # check single level column mux array in single port diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index e03e0308..5340404b 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -18,7 +18,8 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check precharge array in single port debug.info(2, "Checking 3 column precharge") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index f39148d9..873833bd 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,7 +20,8 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 52131505..ad9cfeb2 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -18,7 +18,8 @@ import debug class sense_amp_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index e2fffd04..ad3826a2 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -18,7 +18,8 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py index 8acce579..f61aa144 100755 --- a/compiler/tests/10_write_driver_array_wmask_test.py +++ b/compiler/tests/10_write_driver_array_wmask_test.py @@ -20,7 +20,8 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4") @@ -58,4 +59,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 5c40b146..eb7e3ad9 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -20,7 +20,8 @@ import debug class write_mask_and_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) # check write driver array for single port debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index 0aed8737..eff032a4 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -18,7 +18,8 @@ import debug class dff_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index ad0ab517..18344676 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -18,7 +18,8 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index e8b4a2d9..1183a4ea 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -18,7 +18,8 @@ import debug class dff_buf_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index c297f399..7ff58be4 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -18,7 +18,8 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 2483010b..989fab48 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -18,7 +18,8 @@ import debug class delay_chain_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) diff --git a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py index f4fb5587..579b2805 100755 --- a/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/14_replica_bitcell_1rw_1r_array_test.py @@ -16,7 +16,8 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.bitcell = "bitcell_1rw_1r" OPTS.replica_bitcell = "replica_bitcell_1rw_1r" diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index 4e4d115b..0514d0ce 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -16,7 +16,8 @@ import debug class replica_bitcell_array_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 0146695d..9deadc41 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -16,7 +16,8 @@ import debug class replica_column_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(2, "Testing replica column for 6t_cell") a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 7418f2e8..e81391f2 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -22,7 +22,8 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import control_logic import tech diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 7fcbffd8..677cd271 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -18,7 +18,8 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import control_logic import tech diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py index 7e38c916..0ebb3508 100755 --- a/compiler/tests/18_port_address_test.py +++ b/compiler/tests/18_port_address_test.py @@ -16,7 +16,8 @@ import debug class port_address_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Port address 16 rows") a = factory.create("port_address", cols=16, rows=16) diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index dcaacb0b..4939ad33 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -16,7 +16,8 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py index bfaf4ae3..d486a7fd 100755 --- a/compiler/tests/18_port_data_wmask_test.py +++ b/compiler/tests/18_port_data_wmask_test.py @@ -18,7 +18,8 @@ import debug class port_data_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=16, diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index a4530bf1..27a9a279 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -18,7 +18,8 @@ import debug class bank_select_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index d8f64a37..c7293126 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -19,7 +19,8 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 9a14f741..aa7c5992 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -19,7 +19,8 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 3708940d..d64a5edd 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -19,7 +19,8 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index e4d53de6..bc9f8ff0 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 0d874605..4170e66a 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -18,7 +18,8 @@ import debug class single_bank_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index ad1d2a52..53e32b65 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -18,7 +18,8 @@ import debug class single_bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py index 644678d5..0d70c43e 100755 --- a/compiler/tests/19_single_bank_wmask_test.py +++ b/compiler/tests/19_single_bank_wmask_test.py @@ -18,7 +18,8 @@ import debug class single_bank_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index c6621219..eb885f0b 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") class psram_1bank_2mux_1rw_1w_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 705e6d93..ab475aaf 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -21,7 +21,8 @@ import debug class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" @@ -58,4 +59,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index a619c48e..154fda4e 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index c932a95a..b0dec84b 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error") class psram_1bank_2mux_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index e012ce30..8d4d048f 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -17,8 +17,9 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index b506b87d..5824c60a 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 18c031c9..6cfac474 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -18,8 +18,9 @@ import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): - def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + def runTest(self): + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 3d43bb04..e2d431bf 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 55fe2d0b..dba51753 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -21,7 +21,8 @@ import debug class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, @@ -51,4 +52,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index 4df085e0..823b841a 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -21,7 +21,8 @@ import debug class sram_1bank_32b_1024_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=32, write_size=8, @@ -50,4 +51,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index d849135f..7a77650e 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index bf8ee8f0..ae75618f 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index e056732a..d7ae16a8 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=2, num_words=128, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index cb7dbd9f..ecc44117 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -18,7 +18,8 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index b9bc14a4..c21e6694 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index 26d75d82..71d97db2 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -21,7 +21,8 @@ import debug class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=8, write_size=4, @@ -51,4 +52,4 @@ if __name__ == "__main__": (OPTS, args) = globals.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) - unittest.main(testRunner=debugTestRunner()) \ No newline at end of file + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 61b909ec..b1d54460 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -19,7 +19,8 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index a1ad05a7..c27ab122 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -18,7 +18,8 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index c309b10a..fb81d137 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -18,7 +18,8 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 1b611808..289af76e 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -20,7 +20,8 @@ class model_delay_test(openram_test): """ Compare the accuracy of the analytical model with a spice simulation. """ def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 63ad6022..86cbc518 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -18,7 +18,8 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index c0db881a..37fb56c0 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -18,7 +18,8 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 63d65993..ae9de4f6 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -18,7 +18,8 @@ import debug class psram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index d688d4a0..7d945951 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 6938732c..3173210d 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index a1d1051c..ed7f17fc 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 048ee372..04856d3a 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index c8bd2657..a92ef19e 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index b8d7fc07..538c72e6 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 7133fc71..5a8e5697 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -19,7 +19,8 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index a24610a2..370a4de8 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -19,7 +19,8 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_1w_1r_func_test.py b/compiler/tests/22_sram_wmask_1w_1r_func_test.py index afd8310a..7111299f 100755 --- a/compiler/tests/22_sram_wmask_1w_1r_func_test.py +++ b/compiler/tests/22_sram_wmask_1w_1r_func_test.py @@ -21,7 +21,8 @@ import debug class sram_wmask_1w_1r_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index 8b3fa90d..22c4b29b 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -19,7 +19,8 @@ import debug class sram_wmask_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 5020a5c9..7527fd2b 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -18,7 +18,8 @@ import debug class lib_model_corners_lib_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 399daf7e..dab05941 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -18,7 +18,8 @@ import debug class lib_sram_model_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.netlist_only = True from characterizer import lib diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index cd10fb10..4c9b17ba 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -18,7 +18,8 @@ import debug class lib_sram_prune_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 5a60e9ad..4c5d4ed8 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -17,7 +17,8 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 3390c2e2..bb0a5116 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -18,7 +18,8 @@ import debug class lef_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index e44f081a..ce058f4a 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -17,7 +17,8 @@ import debug class verilog_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py index 7d99120c..da52e8c3 100755 --- a/compiler/tests/26_hspice_pex_pinv_test.py +++ b/compiler/tests/26_hspice_pex_pinv_test.py @@ -20,7 +20,8 @@ import debug class hspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import pinv # load the hspice diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py index 96cc72aa..c1cf97bd 100755 --- a/compiler/tests/26_ngspice_pex_pinv_test.py +++ b/compiler/tests/26_ngspice_pex_pinv_test.py @@ -19,7 +19,8 @@ import debug class ngspice_pex_pinv_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) import pinv # load the ngspice diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index 3fd63117..bc445a68 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -19,7 +19,8 @@ import debug class sram_func_test(openram_test): def runTest(self): - globals.init_openram("{}/config".format(OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) OPTS.use_pex = True diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 16ffbbef..a947ac30 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -20,7 +20,8 @@ class openram_back_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 58b70574..54e2b443 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -20,7 +20,8 @@ class openram_front_end_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/{1}/config".format(OPENRAM_HOME,OPTS.tech_name)) + config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name) + globals.init_openram(config_file) debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.") out_file = "testsram"