Rework bitcells.

Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.

compiler/modules/bitcell_array.py

@@ -62,7 +62,7 @@ class bitcell_array(bitcell_base_array):
             for row in range(self.row_size):
                 name = "bit_r{0}_c{1}".format(row, col)
                 self.cell_inst[row, col]=self.add_inst(name=name,
-                                                    mod=self.cell)
+                                                       mod=self.cell)
                 self.connect_inst(self.get_bitcell_pins(row, col))
 
     def analytical_power(self, corner, load):