mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'lvs' into dev
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commit
c2e258709b
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@ -337,16 +337,25 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False, output_path=
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# Netlists match uniquely.
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# Netlists match uniquely.
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test = re.compile("match uniquely.")
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test = re.compile("match uniquely.")
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correct = list(filter(test.search, final_results))
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uniquely = list(filter(test.search, final_results))
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# Netlists match uniquely.
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test = re.compile("match correctly.")
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correctly = list(filter(test.search, final_results))
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# Fail if they don't match. Something went wrong!
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# Fail if they don't match. Something went wrong!
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if len(correct) == 0:
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if len(uniquely) == 0 and len(correctly) == 0:
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total_errors += 1
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total_errors += 1
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if len(uniquely) == 0 and len(correctly) > 0:
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debug.warning("{0}\tLVS matches but not uniquely".format(cell_name))
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if total_errors>0:
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if total_errors>0:
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# Just print out the whole file, it is short.
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# Just print out the whole file, it is short.
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for e in results:
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for e in results:
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debug.info(1,e.strip("\n"))
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debug.info(1,e.strip("\n"))
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debug.error("{0}\tLVS mismatch (results in {1})".format(cell_name,resultsfile))
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debug.error("{0}\tLVS mismatch (results in {1})".format(cell_name,
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resultsfile))
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else:
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else:
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debug.info(1, "{0}\tLVS matches".format(cell_name))
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debug.info(1, "{0}\tLVS matches".format(cell_name))
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